Megvii Engine Team
|
fc0fcd2f7f
|
chore(winograd): remove winograd transform code
GitOrigin-RevId: 78c3cfceae
|
5 years ago |
Megvii Engine Team
|
a1877ee0fa
|
refactor(dnn): refactor algo interface, use algoinfo instead of global algorithm
GitOrigin-RevId: 479718ac75
|
5 years ago |
Megvii Engine Team
|
f7b2bdae1a
|
refactor(dnn): refactor algorithm type interface
GitOrigin-RevId: 843d885f82
|
5 years ago |
Megvii Engine Team
|
2a3f4d099a
|
refactor(dnn/arm): refactor CPU heuristic algo selection
GitOrigin-RevId: 60d2646bb3
|
5 years ago |
Megvii Engine Team
|
44b27f0d6e
|
build(3516): fix some cpu flags build failed and fix 3516 ycm
GitOrigin-RevId: a0c73fa18a
|
5 years ago |
Megvii Engine Team
|
1f3f4abc38
|
fix(dnn): fix compile warnings
GitOrigin-RevId: 519a6c0c34
|
5 years ago |
Megvii Engine Team
|
343335932a
|
fix(dnn/arm): fix read invalid data in arm kernel
GitOrigin-RevId: f1c4cae667
|
5 years ago |
Megvii Engine Team
|
0380811218
|
feat(dnn/arm_common): add nchw44 8x8x16 stride1 stride2
2x2 3x3 5x5 7x7 directconv
GitOrigin-RevId: 3710182af1
|
5 years ago |
Megvii Engine Team
|
bca00f2e22
|
fix(dnn): midout at where neccessary in megdnn
GitOrigin-RevId: 191334bd96
|
5 years ago |
Megvii Engine Team
|
56381f808b
|
fix(dnn/arm): use vcvtq_f32_s32 for all arm code
GitOrigin-RevId: 27effe7d24
|
5 years ago |
Megvii Engine Team
|
1173205726
|
fix(gopt): nchw_nchwxx useable and opt pass use nchw_nchwxx_valid
GitOrigin-RevId: 60942aca5b
|
5 years ago |
Megvii Engine Team
|
6e70fa7a11
|
feat(dnn/arm): add fp32 asm gemm for a53 a55 and i8i8i16 gemm for a72 a53
GitOrigin-RevId: a049c33f2b
|
5 years ago |
Megvii Engine Team
|
df356635b7
|
fix(mgb/fallback): delete im2col duplicate code and fix nchw44 usable
GitOrigin-RevId: 1aa250e9e7
|
5 years ago |
Megvii Engine Team
|
4a2270834f
|
fix(mgb/fallback): fix conv1x1 and conv1x1_gemv nchw44 usable
GitOrigin-RevId: 90aa75d51e
|
5 years ago |
Megvii Engine Team
|
b778d22523
|
feat(mgb/fallback): add conv1x1_gemv, conv1x1 and im2col 8x8x16/8x8x32 support bias
GitOrigin-RevId: 3d97fedc8f
|
5 years ago |
Megvii Engine Team
|
c357db0134
|
feat(mgb/arm_common): add 8x8x16 nchw44 max pooling
GitOrigin-RevId: ed460adb7a
|
5 years ago |
Megvii Engine Team
|
7f5f375fda
|
feat(dnn/arm): add armv7 nchw_nchw44 3x3s2 asm kernel
GitOrigin-RevId: 50ce91e41d
|
5 years ago |
Megvii Engine Team
|
bcf5691ddf
|
feat(dnn/arm): add nchw_nchw44 i8i8i16 2x2 3x3 5x5 7x7 s1 s2 conv
GitOrigin-RevId: 8ef1541665
|
5 years ago |
Megvii Engine Team
|
a773d07678
|
feat(dnn/arm_common): add nchw44 8x8x16 channel wise conv
stride1 2x2 3x3 5x5 stride2 2x2 3x3 5x5
GitOrigin-RevId: 43d76311c2
|
5 years ago |
Megvii Engine Team
|
7ca3d579db
|
feat(dnn): make mk4 and mk8 matmul for winograd both on aarch64 and armv7 supports n=1
GitOrigin-RevId: 0f64b9f70f
|
5 years ago |
Megvii Engine Team
|
f6018422fd
|
perf(dnn/arm_common): add nchw44 winograd f73
GitOrigin-RevId: 8ed98ab85b
|
5 years ago |
Megvii Engine Team
|
e05c795b45
|
refactor(dnn/arm): refactor direct algo in algo selection
GitOrigin-RevId: d195f44dec
|
5 years ago |
Megvii Engine Team
|
9c475fff17
|
fix(dnn/fallback): delete ConvBias* opr param of conv_bias algo
GitOrigin-RevId: ee5a6874fb
|
5 years ago |
Megvii Engine Team
|
4d56371e0b
|
refactor(dnn/arm): split arm direct kernel to cut compile time
GitOrigin-RevId: b06fba83eb
|
5 years ago |
Megvii Engine Team
|
fff2cdc7bb
|
feat(dnn/fallback): add winograd weight preprocess
GitOrigin-RevId: 4741298e44
|
5 years ago |
Megvii Engine Team
|
d37229fa02
|
feat(dnn): optimize f23 and f63 nchw44 winograd
GitOrigin-RevId: 8569c9dfc6
|
5 years ago |
Megvii Engine Team
|
1e576e321b
|
feat(dnn/aarch64-arm_common): add mat_idx warppespective for aarch64/arm_common/naive
GitOrigin-RevId: 9eb0cdda5c
|
5 years ago |
Megvii Engine Team
|
714cb232bb
|
feat(dnn): add gemv supports in conv1x1 for NCHW44 and NCHW44_DOT(aarch64 binary size grows 2KB)
GitOrigin-RevId: f8b6d7a1b7
|
5 years ago |
Megvii Engine Team
|
32d91d5e6b
|
fix(dnn/arm_common): fix and optimize workspacebundle copy when algo compute
GitOrigin-RevId: 801aedbd72
|
5 years ago |
Megvii Engine Team
|
946a340c3d
|
feat(ci/midout): opt midout and add midout ci
GitOrigin-RevId: 1e5fe75255
|
5 years ago |
Megvii Engine Team
|
cdbe44f8b4
|
feat(dnn): add gemv supports in conv1x1 with format NCHW
GitOrigin-RevId: 97679e8526
|
5 years ago |
Megvii Engine Team
|
80ecabe8c6
|
feat(dnn/arm_common): add nchw_nchw44 aarch64 int8 3x3s2 7x7s2 asm
GitOrigin-RevId: 871465335d
|
5 years ago |
Megvii Engine Team
|
9e904f683b
|
fix(dnn): fix can not inline small function with GCC compiler
GitOrigin-RevId: a23605c9e2
|
5 years ago |
Megvii Engine Team
|
8e9fa80cc2
|
feat(dnn/fallback): add matmul description for im2col
GitOrigin-RevId: 5bde0b60f0
|
5 years ago |
Megvii Engine Team
|
318f6d75fa
|
fix(mge): fix some warnings
GitOrigin-RevId: 38b285f991
|
5 years ago |
Megvii Engine Team
|
a1677d7aa9
|
feat(dnn/arm_common): add fp32 gevm
GitOrigin-RevId: 4d348bbb34
|
5 years ago |
Megvii Engine Team
|
5d950063cf
|
feat(dnn): refactor dot gemv for both aarch64 and aarch32
GitOrigin-RevId: 2b98867e45
|
5 years ago |
Megvii Engine Team
|
48ac1e1abd
|
feat(dnn/fallback): delete nopack onlypacka noneed datatype,and add
im2co and conv1x1 mk4_dot support
GitOrigin-RevId: 096b16a3ab
|
5 years ago |
Megvii Engine Team
|
3117bfb738
|
fix(dnn/arm): nchw44 direct int8 support 8832
GitOrigin-RevId: 696fa05d94
|
5 years ago |
Megvii Engine Team
|
273f891b55
|
fix(mgb/gopt): fix run-time winograd-transform and nchwxx error
GitOrigin-RevId: aca796f17d
|
5 years ago |
Megvii Engine Team
|
02abc36ea6
|
fix(mbg/arm_common): fix nchw44-dot misc issue
GitOrigin-RevId: f870ad964c
|
5 years ago |
Megvii Engine Team
|
9ed3882a94
|
fix(opr/dnn): fix winograd fast run mismatch
GitOrigin-RevId: d308085b9f
|
5 years ago |
Megvii Engine Team
|
18be23f328
|
fix(mbg/gopt): fix nchwxx gopt with no fuse conv_bias and winograd
fast-run
GitOrigin-RevId: 49ccbdf2d4
|
5 years ago |
Megvii Engine Team
|
7b0dbe6af8
|
fix(dnn/arm): fix stride 1 support for int8 nchw_nchw44
GitOrigin-RevId: 9d718eb7a4
|
5 years ago |
Megvii Engine Team
|
198f3eb5f6
|
fix(dnn/arm): fix fp32 nchw44 direct workspace bug
GitOrigin-RevId: 6ee433b02c
|
5 years ago |
Megvii Engine Team
|
9e876203b5
|
feat(dnn): add int8 direct conv dot nchw44
GitOrigin-RevId: 31830ba7a4
|
5 years ago |
Megvii Engine Team
|
09ceaaaecf
|
fix(dnn/arm): stride1 support for nchw_nchw44 fp32 conv
GitOrigin-RevId: 744c5db3dc
|
5 years ago |
Megvii Engine Team
|
4f8e60801c
|
feat(dnn): fix Werror by adding macro
GitOrigin-RevId: 1f5fe4d46a
|
5 years ago |
Megvii Engine Team
|
8f87a3e988
|
feat(dnn/arm_common): add int8 nchw44 winograd f23_4x4 f23_8x8 compute float32/int16 output int8
GitOrigin-RevId: d99ef7efcd
|
5 years ago |
Megvii Engine Team
|
6c29548d20
|
fix(dnn/arm): fix nchw_nchw44 dot stride1 support
GitOrigin-RevId: c8d3d55b25
|
5 years ago |