ref https://gitlab.freedesktop.org/mesa/mesa/-/issues/10847

* x86 vulkan fallback
* comment about bf16s

* quantize gemm

* write gemm quantize scales

* update doc

* less openmp args

* x86 riscv fallback

* skip gemm vulkan int8

* fix noint8 test, fix arm bf16 test

* enable vfpv4 on neon build only

* fix gemm vulkan without C

* fp16 pack8 output

* enable elempack=8 only for asimdhp+

* tiled gemm int8 test

* opt arm64 tiles, fix asimdhp dispatch

* pnnx convert onnx resize with roi, torch.max torch.min with dim returns tuple

* torch max min only support single dim

* release ubuntu 24.04 package, major release yml refactor

* update macos vulkan sdk

* set MACOSX_DEPLOYMENT_TARGET

* update onnx proto

Bumps [pypa/cibuildwheel](https://github.com/pypa/cibuildwheel) from 2.17.0 to 2.20.0.
- [Release notes](https://github.com/pypa/cibuildwheel/releases)
- [Changelog](https://github.com/pypa/cibuildwheel/blob/main/docs/changelog.md)
- [Commits](https://github.com/pypa/cibuildwheel/compare/v2.17.0...v2.20.0)

---
updated-dependencies:
- dependency-name: pypa/cibuildwheel
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>

Enable policy CMP0057 for cmake version >= 3.3

Depending on the arch, ldr/str can be faster than ld1/st1, especially
for loading to one lane form. For example, on Cortex A75,

1. execution latency of 'ldr q0' and 'ldr h0' are 5
2. execution latency of 'ld1 {v0.16b}' is 6
3. execution latency of 'ld1 {v0.h}[0]' is 8

On Cortex X3,
1. execution latency of 'ldr q0' and 'ldr h0' are 6
2. execution latency of 'ld1 {v0.16b}' is 6
3. execution latency of 'ld1 {v0.h}[0]' is 8

Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>

* Fix tanh typo for rvv.

* Fix tanh for rvv fp16.