The forced values for LIBNAME were either riscv64_generic or c910v
while the non-forced value of LIBNAME was always riscv64.

The crash is reproducible when building OpenBLAS without forcing a
target in a riscv64 container running on an X86_64 machine with an
older version of QEMU, e.g., 7.0.0, registered with binfmt_misc to
run riscv64 binaries.  With this setup, cat /proc/cpuinfo in the
container returns the cpu information for the host, which contains a
"model name" string, and we execute the buggy code.  The code in
question is searching in an uninitialised buffer for the ':' character
and doesn't check to see whether it was found or not.  This can result
in pmodel containing the pointer value 1 and a crash when pmodel is
defererenced.  The algorithm to detect the C910V CPU has not been
modified, merely fixed to prevent the crash.

A few additional checks for NULL pointers are added to improve the
robustness of the code and a whitespace error is corrected.

Update T-Head toolchains v2.8.0

Signed-off-by: Han Gao/Revy/Rabenda <rabenda.cn@gmail.com>

Add dynamic support for Arm(R) Neoverse(TM) V2 processor

Whilst I figure out how best to map the L2 parameters without
duplicating all of `ARMV8SVE`, lets just map this to `NEOVERSEV1`.

Fix utest compilation

Introduced recently when adding new test cases for ZSCAL

- include cblas is needed for cblas_zscal
- ASSERT macro does not exist
- missing closing )

Add CSKY support

Increase multithreading threshold for S/DGEMV by a factor of 50

* Support ArmCompilerforLinux as classic flang

Fix Clang sapphire rapids march flag

Only use mtune=native in ARM64 fallback paths when not cross-compiling

Handle NAN and INF in ARM and generic/s390x ZSCAL

Add BLAS extension openblas_set_num_threads_local()

Tweak LAPACK tests for SGS/DGS to avoid spurious errors resulting from FMA-induced inaccuracies

Fix typo in common.h

Check compiler support for AVX512BF16 and base COL/SPR kernel choice on that

[WIP] Add fixes and utests for ZSCAL with NaN or Inf arguments

Replace two vector loads with one vector pair load and fix endianess of stores - DGEMM PowerPC versions.

Revert accidental direct commits to develop