MOD: optimize DGEMM of large matrices on cortex A53 & A55

cmake: Set SUFFIX64 also for NOFORTRAN

Fix MIPS/MIPS64 compilation querying compiler rather than cpu for MSA capability

Fix potentially wrong HOSTARCH definition in cross-compilation

Fix NULL pointer checks in blas_memory_alloc

Fix exported OpenBLASTargets.cmake

Add CPUID recognition of Intel Alder Lake

Adjust compiler options for nvc after 21.9 (and fix typo in DYNAMIC_ARCH settings)

Fix flipped indices in benchmark for gemv

*  return OMP places (if available, or SC_NPROCESSORS_CONF) for maximum thread count when built with OpenMP

Fixes #3439

cpuid_zarch/hwcaps: add documentation and dump hwcaps in init

Add cblas_{c/z}srot cblas_{c/z}rotg support

When both BUILD_SHARED_LIBS and BUILD_STATIC_LIBS are enabled,
cmake export both of them to OpenBLASTargets under tha same name `OpenBLAS::OpenBLAS`
which leads to fatal error about OpenBLAS::OpenBLAS being both static and shared target.
This change makes cmake export only the shared library in that case.
There is another solution to treat them as components,
but I am afraid that will make it backward incompatible.

Add pointers to the definition of the hardware capability flags in glibc
and describe how they relate to the levels CPU_Z13 and CPU_Z14 for
optimized kernels.

To aid identifying available hardware capabilities and in debugging
potential build issues, dump their value in dynamic_arch_init() when
OPENBLAS_VERBOSE is set to 2 or higher.

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>

Add runtime DYNAMIC_ARCH cpu detection for Tiger Lake H

auto-detect for Intel i7-11800H

s390x: use DYNAMIC_ARCH's cpu detection for compile-time choice

On s390x, the run-time detection for DYNAMIC_ARCH and the compile-time
choice in cpuid_zarch use different methods for identifying the
supported CPU features. To make cpuid_zarch future-proof and both easier
to maintain, switch cpuid_zarch to the same mechanism as DYNAMIC_ZARCH
(i.e., derive the supported CPU features from hwcap flags) and share
code between both (in a new header cpuid_zarch.h).

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>

Revert invalid trsv shortcut from PR #3252

Revert wrong ZTRSV optimization from #3252

Enable SVE for A64FX

* Add initial support for Fujitsu A64FX as generic ARMV8

sbgemm: add AMX-BF16 based kernel for Sapphire Rapids