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OpenBLAS/TargetList.txt

TargetList.txt 703 B
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Added docs for make TARGET=your_cpu_target.
14 years ago
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TargetList.txt: minor re-ordering
13 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Init Sandybridge codes based on Nehalem.
14 years ago
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
11 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Refs #113. Fixed the typo BOBCATE -> BOBCAT
13 years ago
Added BULLDOZER target. So far it uses barcelona kernels.
13 years ago
Update the doc for target list.
11 years ago
added target processor STEAMROLLER
11 years ago
Add AMD Excavator target.
10 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Add POWER7/POWER8 as targets
10 years ago
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Added docs for make TARGET=your_cpu_target.
14 years ago
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MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Added docs for make TARGET=your_cpu_target.
14 years ago
​
Init Sandybridge codes based on Nehalem.
14 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
​
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
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Update the doc for target list.
11 years ago
​
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Add ARM targets.
11 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
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  1. Force Target Examples:

  2. 

  3. make TARGET=NEHALEM

  4. make TARGET=LOONGSON3A BINARY=64

  5. make TARGET=ISTANBUL

  6. 

  7. Supported List:

  8. 1.X86/X86_64

  9. a)Intel CPU:

  10. P2

  11. KATMAI

  12. COPPERMINE

  13. NORTHWOOD

  14. PRESCOTT

  15. BANIAS

  16. YONAH

  17. CORE2

  18. PENRYN

  19. DUNNINGTON

  20. NEHALEM

  21. SANDYBRIDGE

  22. HASWELL

  23. ATOM

  24. 

  25. b)AMD CPU:

  26. ATHLON

  27. OPTERON

  28. OPTERON_SSE3

  29. BARCELONA

  30. SHANGHAI

  31. ISTANBUL

  32. BOBCAT

  33. BULLDOZER

  34. PILEDRIVER

  35. STEAMROLLER

  36. EXCAVATOR

  37. 

  38. c)VIA CPU:

  39. SSE_GENERIC

  40. VIAC3

  41. NANO

  42. 

  43. 2.Power CPU:

  44. POWER4

  45. POWER5

  46. POWER6

  47. POWER7

  48. POWER8

  49. PPCG4

  50. PPC970

  51. PPC970MP

  52. PPC440

  53. PPC440FP2

  54. CELL

  55. 

  56. 3.MIPS CPU:

  57. P5600

  58. 

  59. 4.MIPS64 CPU:

  60. SICORTEX

  61. LOONGSON3A

  62. LOONGSON3B

  63. I6400

  64. 

  65. 5.IA64 CPU:

  66. ITANIUM2

  67. 

  68. 6.SPARC CPU:

  69. SPARC

  70. SPARCV7

  71. 

  72. 7.ARM CPU:

  73. CORTEXA15

  74. CORTEXA9

  75. ARMV7

  76. ARMV6

  77. ARMV5

  78. 

  79. 8.ARM 64-bit CPU:

  80. ARMV8

  81. CORTEXA57

  82.

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.