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mindspore2022/mindspore/lite/nnacl/assembly/arm64/PostFuncBiasReluC8.S

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  1. #ifdef __aarch64__

  2. 

  3.     .text

  4.     .align 5

  5.     //.p2align 5,,15

  6.     .global PostFuncBiasReluC8

  7. #ifndef __APPLE__

  8.     .type PostFuncBiasReluC8, %function

  9. #endif

  10. 

  11. //void PostFuncBiasReluC8(float *dst, const float *src, const float *bias, size_t oc8div,size_t oc8mod

  12. //                        size_t plane_size, size_t stride, int relu_type);

  13. // x0 dst           x1 srx           x2 bias

  14. // x3 oc8div        x4 oc8mod        x5 plane_size

  15. // x6 stride        x7 relu_type

  16. 

  17. // v0 ~ v15 value

  18. // v16  v17 bias data

  19. // x14  x15  weite loop tmp buf

  20. // x16  relu6  #6;    x17 relu #0

  21. // w10  oc8 loop control

  22. // w13  hw  loop control

  23. 

  24. PostFuncBiasReluC8:

  25.   sub sp, sp, #128

  26.   st1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp], #64

  27.   st1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp], #64

  28. 

  29.   movi v26.4s, #6

  30.   scvtf v26.4s, v26.4s

  31.   dup v27.4s, wzr

  32.   mov w10, #0

  33. 

  34. Loop_C8:

  35.   cmp w10, w3

  36.   beq Loop_C1

  37.   mov x15,  #4

  38.   mul x14, x10, x15

  39.   add x15, x0, x14

  40.   add w10, w10, #8

  41.   mov w13, w5

  42.   ld1 {v16.4s, v17.4s}, [x2], #32

  43. 

  44. Loop_8x8:

  45.   cmp w13, #8

  46.   blt Loop_4x8

  47.   sub w13, w13, #8

  48.   ld1 {v0.4s, v1.4s, v2.4s, v3.4s}, [x1], #64

  49.   ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64

  50.   ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [x1], #64

  51.   ld1 {v12.4s, v13.4s, v14.4s, v15.4s}, [x1], #64

  52. 

  53.   fadd v0.4s, v0.4s, v16.4s

  54.   fadd v1.4s, v1.4s, v17.4s

  55.   fadd v2.4s, v2.4s, v16.4s

  56.   fadd v3.4s, v3.4s, v17.4s

  57.   fadd v4.4s, v4.4s, v16.4s

  58.   fadd v5.4s, v5.4s, v17.4s

  59.   fadd v6.4s, v6.4s, v16.4s

  60.   fadd v7.4s, v7.4s, v17.4s

  61.   fadd v8.4s, v8.4s, v16.4s

  62.   fadd v9.4s, v9.4s, v17.4s

  63.   fadd v10.4s, v10.4s, v16.4s

  64.   fadd v11.4s, v11.4s, v17.4s

  65.   fadd v12.4s, v12.4s, v16.4s

  66.   fadd v13.4s, v13.4s, v17.4s

  67.   fadd v14.4s, v14.4s, v16.4s

  68.   fadd v15.4s, v15.4s, v17.4s

  69. 

  70.   cmp x7, #3

  71.   beq Relu6_8x8

  72.   cmp x7, #1

  73.   beq Relu_8x8

  74.   b Write_8x8

  75. Relu6_8x8:

  76.   fmin v0.4s, v0.4s, v26.4s

  77.   fmin v1.4s, v1.4s, v26.4s

  78.   fmin v2.4s, v2.4s, v26.4s

  79.   fmin v3.4s, v3.4s, v26.4s

  80.   fmin v4.4s, v4.4s, v26.4s

  81.   fmin v5.4s, v5.4s, v26.4s

  82.   fmin v6.4s, v6.4s, v26.4s

  83.   fmin v7.4s, v7.4s, v26.4s

  84.   fmin v8.4s, v8.4s, v26.4s

  85.   fmin v9.4s, v9.4s, v26.4s

  86.   fmin v10.4s, v10.4s, v26.4s

  87.   fmin v11.4s, v11.4s, v26.4s

  88.   fmin v12.4s, v12.4s, v26.4s

  89.   fmin v13.4s, v13.4s, v26.4s

  90.   fmin v14.4s, v14.4s, v26.4s

  91.   fmin v15.4s, v15.4s, v26.4s

  92. Relu_8x8:

  93.   fmax v0.4s, v0.4s, v27.4s

  94.   fmax v1.4s, v1.4s, v27.4s

  95.   fmax v2.4s, v2.4s, v27.4s

  96.   fmax v3.4s, v3.4s, v27.4s

  97.   fmax v4.4s, v4.4s, v27.4s

  98.   fmax v5.4s, v5.4s, v27.4s

  99.   fmax v6.4s, v6.4s, v27.4s

  100.   fmax v7.4s, v7.4s, v27.4s

  101.   fmax v8.4s, v8.4s, v27.4s

  102.   fmax v9.4s, v9.4s, v27.4s

  103.   fmax v10.4s, v10.4s, v27.4s

  104.   fmax v11.4s, v11.4s, v27.4s

  105.   fmax v12.4s, v12.4s, v27.4s

  106.   fmax v13.4s, v13.4s, v27.4s

  107.   fmax v14.4s, v14.4s, v27.4s

  108.   fmax v15.4s, v15.4s, v27.4s

  109. Write_8x8:

  110.   st1 {v0.4s, v1.4s}, [x15], x6

  111.   st1 {v2.4s, v3.4s}, [x15], x6

  112.   st1 {v4.4s, v5.4s}, [x15], x6

  113.   st1 {v6.4s, v7.4s}, [x15], x6

  114.   st1 {v8.4s, v9.4s}, [x15], x6

  115.   st1 {v10.4s, v11.4s}, [x15], x6

  116.   st1 {v12.4s, v13.4s}, [x15], x6

  117.   st1 {v14.4s, v15.4s}, [x15], x6

  118.   b Loop_8x8

  119. 

  120. Loop_4x8:

  121.   cmp w13, #4

  122.   blt Loop_1x8

  123.   sub w13, w13, #4

  124.   ld1 {v0.4s, v1.4s, v2.4s, v3.4s}, [x1], #64

  125.   ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64

  126. 

  127.   fadd v0.4s, v0.4s, v16.4s

  128.   fadd v1.4s, v1.4s, v17.4s

  129.   fadd v2.4s, v2.4s, v16.4s

  130.   fadd v3.4s, v3.4s, v17.4s

  131.   fadd v4.4s, v4.4s, v16.4s

  132.   fadd v5.4s, v5.4s, v17.4s

  133.   fadd v6.4s, v6.4s, v16.4s

  134.   fadd v7.4s, v7.4s, v17.4s

  135. 

  136.   cmp x7, #3

  137.   beq Relu6_4x8

  138.   cmp x7, #1

  139.   beq Relu_4x8

  140.   b Write_4x8

  141. Relu6_4x8:

  142.   fmin v0.4s, v0.4s, v26.4s

  143.   fmin v1.4s, v1.4s, v26.4s

  144.   fmin v2.4s, v2.4s, v26.4s

  145.   fmin v3.4s, v3.4s, v26.4s

  146.   fmin v4.4s, v4.4s, v26.4s

  147.   fmin v5.4s, v5.4s, v26.4s

  148.   fmin v6.4s, v6.4s, v26.4s

  149.   fmin v7.4s, v7.4s, v26.4s

  150. Relu_4x8:

  151.   fmax v0.4s, v0.4s, v27.4s

  152.   fmax v1.4s, v1.4s, v27.4s

  153.   fmax v2.4s, v2.4s, v27.4s

  154.   fmax v3.4s, v3.4s, v27.4s

  155.   fmax v4.4s, v4.4s, v27.4s

  156.   fmax v5.4s, v5.4s, v27.4s

  157.   fmax v6.4s, v6.4s, v27.4s

  158.   fmax v7.4s, v7.4s, v27.4s

  159. Write_4x8:

  160.   st1 {v0.4s, v1.4s}, [x15], x6

  161.   st1 {v2.4s, v3.4s}, [x15], x6

  162.   st1 {v4.4s, v5.4s}, [x15], x6

  163.   st1 {v6.4s, v7.4s}, [x15], x6

  164. 

  165. Loop_1x8:

  166.   cmp x7, #3

  167.   beq Relu6_1x8

  168.   cmp x7, #1

  169.   beq Relu_1x8

  170.   b Write_1x8

  171. Relu6_1x8:

  172.   cmp w13, #0

  173.   beq Loop_C8

  174.   sub w13, w13, #1

  175.   ld1 {v0.4s, v1.4s}, [x1], #32

  176.   fadd v0.4s, v0.4s, v16.4s

  177.   fadd v1.4s, v1.4s, v17.4s

  178.   fmin v0.4s, v0.4s, v26.4s

  179.   fmin v1.4s, v1.4s, v26.4s

  180.   fmax v0.4s, v0.4s, v27.4s

  181.   fmax v1.4s, v1.4s, v27.4s

  182.   st1 {v0.4s, v1.4s}, [x15], x6

  183.   b Relu6_1x8

  184. Relu_1x8:

  185.   cmp w13, #0

  186.   beq Loop_C8

  187.   sub w13, w13, #1

  188.   ld1 {v0.4s, v1.4s}, [x1], #32

  189.   fadd v0.4s, v0.4s, v16.4s

  190.   fadd v1.4s, v1.4s, v17.4s

  191.   fmax v0.4s, v0.4s, v27.4s

  192.   fmax v1.4s, v1.4s, v27.4s

  193.   st1 {v0.4s, v1.4s}, [x15], x6

  194.   b Relu_1x8

  195. Write_1x8:

  196.   cmp w13, #0

  197.   beq Loop_C8

  198.   sub w13, w13, #1

  199.   ld1 {v0.4s, v1.4s}, [x1], #32

  200.   fadd v0.4s, v0.4s, v16.4s

  201.   fadd v1.4s, v1.4s, v17.4s

  202.   st1 {v0.4s, v1.4s}, [x15], x6

  203.   b Write_1x8

  204. 

  205. 

  206. Loop_C1:

  207.   cmp x4, #0

  208.   beq End

  209.   mov w13, w5

  210.   ld1 {v16.4s, v17.4s}, [x2], #32

  211.   mov x15,  #4

  212.   mul x14, x10, x15

  213.   add x0, x0, x14

  214. 

  215.   cmp x4, #1

  216.   beq Loop_C1_1

  217.   cmp x4, #2

  218.   beq Loop_C1_2

  219.   cmp x4, #3

  220.   beq Loop_C1_3

  221.   cmp x4, #4

  222.   beq Loop_C1_4

  223.   cmp x4, #5

  224.   beq Loop_C1_5

  225.   cmp x4, #6

  226.   beq Loop_C1_6

  227.   cmp x4, #7

  228.   beq Loop_C1_7

  229. 

  230. Loop_C1_1:

  231.   cmp x7, #3

  232.   beq Loop_C1_1_Relu6

  233.   cmp x7, #1

  234.   beq Loop_C1_1_Relu

  235.   b Loop_C1_1_Write

  236. Loop_C1_1_Relu6:

  237.   cmp w13, #0

  238.   beq End

  239.   sub w13, w13, #1

  240.   ld1 {v0.4s, v1.4s}, [x1], #32

  241.   fadd v0.4s, v0.4s, v16.4s

  242.   fmin v0.4s, v0.4s, v26.4s

  243.   fmax v0.4s, v0.4s, v27.4s

  244.   str s0, [x0]

  245.   add x0, x0, x6

  246.   b Loop_C1_1_Relu6

  247. Loop_C1_1_Relu:

  248.   cmp w13, #0

  249.   beq End

  250.   sub w13, w13, #1

  251.   ld1 {v0.4s, v1.4s}, [x1], #32

  252.   fadd v0.4s, v0.4s, v16.4s

  253.   fmax v0.4s, v0.4s, v27.4s

  254.   str s0, [x0]

  255.   add x0, x0, x6

  256.   b Loop_C1_1_Relu

  257. Loop_C1_1_Write:

  258.   cmp w13, #0

  259.   beq End

  260.   sub w13, w13, #1

  261.   ld1 {v0.4s, v1.4s}, [x1], #32

  262.   fadd v0.4s, v0.4s, v16.4s

  263.   str s0, [x0]

  264.   add x0, x0, x6

  265.   b Loop_C1_1_Write

  266. 

  267. Loop_C1_2:

  268.   cmp x7, #3

  269.   beq Loop_C1_2_Relu6

  270.   cmp x7, #1

  271.   beq Loop_C1_2_Relu

  272.   b Loop_C1_2_Write

  273. Loop_C1_2_Relu6:

  274.   cmp w13, #0

  275.   beq End

  276.   sub w13, w13, #1

  277.   ld1 {v0.4s, v1.4s}, [x1], #32

  278.   fadd v0.4s, v0.4s, v16.4s

  279.   fmin v0.4s, v0.4s, v26.4s

  280.   fmax v0.4s, v0.4s, v27.4s

  281.   dup s1, v0.s[1]

  282.   stp s0, s1, [x0]

  283.   add x0, x0, x6

  284.   b Loop_C1_2_Relu6

  285. Loop_C1_2_Relu:

  286.   cmp w13, #0

  287.   beq End

  288.   sub w13, w13, #1

  289.   ld1 {v0.4s, v1.4s}, [x1], #32

  290.   fadd v0.4s, v0.4s, v16.4s

  291.   fmax v0.4s, v0.4s, v27.4s

  292.   dup s1, v0.s[1]

  293.   stp s0, s1, [x0]

  294.   add x0, x0, x6

  295.   b Loop_C1_2_Relu

  296. Loop_C1_2_Write:

  297.   cmp w13, #0

  298.   beq End

  299.   sub w13, w13, #1

  300.   ld1 {v0.4s, v1.4s}, [x1], #32

  301.   fadd v0.4s, v0.4s, v16.4s

  302.   dup s1, v0.s[1]

  303.   stp s0, s1, [x0]

  304.   add x0, x0, x6

  305.   b Loop_C1_2_Write

  306. 

  307. 

  308. Loop_C1_3:

  309.   add x15, x0, #8

  310.   cmp x7, #3

  311.   beq Loop_C1_3_Relu6

  312.   cmp x7, #1

  313.   beq Loop_C1_3_Relu

  314.   b Loop_C1_3_Write

  315. Loop_C1_3_Relu6:

  316.   cmp w13, #0

  317.   beq End

  318.   sub w13, w13, #1

  319.   ld1 {v0.4s, v1.4s}, [x1], #32

  320.   fadd v0.4s, v0.4s, v16.4s

  321.   fmin v0.4s, v0.4s, v26.4s

  322.   fmax v0.4s, v0.4s, v27.4s

  323.   dup s1, v0.s[1]

  324.   stp s0, s1, [x0]

  325.   add x0, x0, x6

  326.   st1 {v0.s}[2], [x15], x6

  327.   b Loop_C1_3_Relu6

  328. Loop_C1_3_Relu:

  329.   cmp w13, #0

  330.   beq End

  331.   sub w13, w13, #1

  332.   ld1 {v0.4s, v1.4s}, [x1], #32

  333.   fadd v0.4s, v0.4s, v16.4s

  334.   fmax v0.4s, v0.4s, v27.4s

  335.   dup s1, v0.s[1]

  336.   stp s0, s1, [x0]

  337.   add x0, x0, x6

  338.   st1 {v0.s}[2], [x15], x6

  339.   b Loop_C1_3_Relu

  340. Loop_C1_3_Write:

  341.   cmp w13, #0

  342.   beq End

  343.   sub w13, w13, #1

  344.   ld1 {v0.4s, v1.4s}, [x1], #32

  345.   fadd v0.4s, v0.4s, v16.4s

  346.   dup s1, v0.s[1]

  347.   stp s0, s1, [x0]

  348.   add x0, x0, x6

  349.   st1 {v0.s}[2], [x15], x6

  350.   b Loop_C1_3_Write

  351. 

  352. Loop_C1_4:

  353.   cmp x7, #3

  354.   beq Loop_C1_4_Relu6

  355.   cmp x7, #1

  356.   beq Loop_C1_4_Relu

  357.   b Loop_C1_4_Write

  358. Loop_C1_4_Relu6:

  359.   cmp w13, #0

  360.   beq End

  361.   sub w13, w13, #1

  362.   ld1 {v0.4s, v1.4s}, [x1], #32

  363.   fadd v0.4s, v0.4s, v16.4s

  364.   fmin v0.4s, v0.4s, v26.4s

  365.   fmax v0.4s, v0.4s, v27.4s

  366.   st1 {v0.4s}, [x0], x6

  367.   b Loop_C1_4_Relu6

  368. Loop_C1_4_Relu:

  369.   cmp w13, #0

  370.   beq End

  371.   sub w13, w13, #1

  372.   ld1 {v0.4s, v1.4s}, [x1], #32

  373.   fadd v0.4s, v0.4s, v16.4s

  374.   fmax v0.4s, v0.4s, v27.4s

  375.   st1 {v0.4s}, [x0], x6

  376.   b Loop_C1_4_Relu6

  377. Loop_C1_4_Write:

  378.   cmp w13, #0

  379.   beq End

  380.   sub w13, w13, #1

  381.   ld1 {v0.4s, v1.4s}, [x1], #32

  382.   fadd v0.4s, v0.4s, v16.4s

  383.   st1 {v0.4s}, [x0], x6

  384.   b Loop_C1_4_Write

  385. 

  386. Loop_C1_5:

  387.   add x15, x0, #16

  388.   cmp x7, #3

  389.   beq Loop_C1_5_Relu6

  390.   cmp x7, #1

  391.   beq Loop_C1_5_Relu

  392.   b Loop_C1_5_Write

  393. Loop_C1_5_Relu6:

  394.   cmp w13, #0

  395.   beq End

  396.   sub w13, w13, #1

  397.   ld1 {v0.4s, v1.4s}, [x1], #32

  398.   fadd v0.4s, v0.4s, v16.4s

  399.   fadd v1.4s, v1.4s, v17.4s

  400.   fmin v0.4s, v0.4s, v26.4s

  401.   fmin v1.4s, v1.4s, v26.4s

  402.   fmax v0.4s, v0.4s, v27.4s

  403.   fmax v1.4s, v1.4s, v27.4s

  404.   st1 {v0.4s}, [x0], x6

  405.   str s1, [x15]

  406.   add x15, x15, x6

  407.   b Loop_C1_5_Relu6

  408. Loop_C1_5_Relu:

  409.   cmp w13, #0

  410.   beq End

  411.   sub w13, w13, #1

  412.   ld1 {v0.4s, v1.4s}, [x1], #32

  413.   fadd v0.4s, v0.4s, v16.4s

  414.   fadd v1.4s, v1.4s, v17.4s

  415.   fmax v0.4s, v0.4s, v27.4s

  416.   fmax v1.4s, v1.4s, v27.4s

  417.   st1 {v0.4s}, [x0], x6

  418.   str s1, [x15]

  419.   add x15, x15, x6

  420.   b Loop_C1_5_Relu

  421. Loop_C1_5_Write:

  422.   cmp w13, #0

  423.   beq End

  424.   sub w13, w13, #1

  425.   ld1 {v0.4s, v1.4s}, [x1], #32

  426.   fadd v0.4s, v0.4s, v16.4s

  427.   fadd v1.4s, v1.4s, v17.4s

  428.   st1 {v0.4s}, [x0], x6

  429.   str s1, [x15]

  430.   add x15, x15, x6

  431.   b Loop_C1_5_Write

  432. 

  433. Loop_C1_6:

  434.   add x15, x0, #16

  435.   cmp x7, #3

  436.   beq Loop_C1_6_Relu6

  437.   cmp x7, #1

  438.   beq Loop_C1_6_Relu

  439.   b Loop_C1_6_Write

  440. Loop_C1_6_Relu6:

  441.   cmp w13, #0

  442.   beq End

  443.   sub w13, w13, #1

  444.   ld1 {v0.4s, v1.4s}, [x1], #32

  445.   fadd v0.4s, v0.4s, v16.4s

  446.   fadd v1.4s, v1.4s, v17.4s

  447.   fmin v0.4s, v0.4s, v26.4s

  448.   fmin v1.4s, v1.4s, v26.4s

  449.   fmax v0.4s, v0.4s, v27.4s

  450.   fmax v1.4s, v1.4s, v27.4s

  451.   st1 {v0.4s}, [x0], x6

  452.   dup s0, v1.s[1]

  453.   stp s1, s0, [x15]

  454.   add x15, x15, x6

  455.   b Loop_C1_6_Relu6

  456. Loop_C1_6_Relu:

  457.   cmp w13, #0

  458.   beq End

  459.   sub w13, w13, #1

  460.   ld1 {v0.4s, v1.4s}, [x1], #32

  461.   fadd v0.4s, v0.4s, v16.4s

  462.   fadd v1.4s, v1.4s, v17.4s

  463.   fmax v0.4s, v0.4s, v27.4s

  464.   fmax v1.4s, v1.4s, v27.4s

  465.   st1 {v0.4s}, [x0], x6

  466.   dup s0, v1.s[1]

  467.   stp s1, s0, [x15]

  468.   add x15, x15, x6

  469.   b Loop_C1_6_Relu

  470. Loop_C1_6_Write:

  471.   cmp w13, #0

  472.   beq End

  473.   sub w13, w13, #1

  474.   ld1 {v0.4s, v1.4s}, [x1], #32

  475.   fadd v0.4s, v0.4s, v16.4s

  476.   fadd v1.4s, v1.4s, v17.4s

  477.   st1 {v0.4s}, [x0], x6

  478.   dup s0, v1.s[1]

  479.   stp s1, s0, [x15]

  480.   add x15, x15, x6

  481.   b Loop_C1_6_Write

  482. 

  483. Loop_C1_7:

  484.   add x15, x0, #16

  485.   add x14, x0, #24

  486.   cmp x7, #3

  487.   beq Loop_C1_7_Relu6

  488.   cmp x7, #1

  489.   beq Loop_C1_7_Relu

  490.   b Loop_C1_7_Write

  491. Loop_C1_7_Relu6:

  492.   cmp w13, #0

  493.   beq End

  494.   sub w13, w13, #1

  495.   ld1 {v0.4s, v1.4s}, [x1], #32

  496.   fadd v0.4s, v0.4s, v16.4s

  497.   fadd v1.4s, v1.4s, v17.4s

  498.   fmin v0.4s, v0.4s, v26.4s

  499.   fmin v1.4s, v1.4s, v26.4s

  500.   fmax v0.4s, v0.4s, v27.4s

  501.   fmax v1.4s, v1.4s, v27.4s

  502.   st1 {v0.4s}, [x0], x6

  503.   dup s0, v1.s[1]

  504.   stp s1, s0, [x15]

  505.   add x15, x15, x6

  506.   st1 {v1.s}[2], [x14], x6

  507.   b Loop_C1_7_Relu6

  508. Loop_C1_7_Relu:

  509.   cmp w13, #0

  510.   beq End

  511.   sub w13, w13, #1

  512.   ld1 {v0.4s, v1.4s}, [x1], #32

  513.   fadd v0.4s, v0.4s, v16.4s

  514.   fadd v1.4s, v1.4s, v17.4s

  515.   fmax v0.4s, v0.4s, v27.4s

  516.   fmax v1.4s, v1.4s, v27.4s

  517.   st1 {v0.4s}, [x0], x6

  518.   dup s0, v1.s[1]

  519.   stp s1, s0, [x15]

  520.   add x15, x15, x6

  521.   st1 {v1.s}[2], [x14], x6

  522.   b Loop_C1_7_Relu

  523. Loop_C1_7_Write:

  524.   cmp w13, #0

  525.   beq End

  526.   sub w13, w13, #1

  527.   ld1 {v0.4s, v1.4s}, [x1], #32

  528.   fadd v0.4s, v0.4s, v16.4s

  529.   fadd v1.4s, v1.4s, v17.4s

  530.   st1 {v0.4s}, [x0], x6

  531.   dup s0, v1.s[1]

  532.   stp s1, s0, [x15]

  533.   add x15, x15, x6

  534.   st1 {v1.s}[2], [x14], x6

  535.   b Loop_C1_7_Write

  536. 

  537. End:

  538.   sub sp, sp, #128

  539.   ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp], #64

  540.   ld1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp], #64

  541.   ret

  542. #endif