diff --git a/dnn/src/arm_common/elemwise_helper/kimpl/typecvt.h b/dnn/src/arm_common/elemwise_helper/kimpl/typecvt.h index c52a8c5d..15c5e106 100644 --- a/dnn/src/arm_common/elemwise_helper/kimpl/typecvt.h +++ b/dnn/src/arm_common/elemwise_helper/kimpl/typecvt.h @@ -19,7 +19,6 @@ namespace arm_common { template struct TypeCvtOp; -#if __ARM_ARCH >= 8 template <> struct TypeCvtOp : UnaryOpBase { using UnaryOpBase::UnaryOpBase; @@ -55,59 +54,6 @@ struct TypeCvtOp : UnaryOpBase { return QConverter::convert(vitem0); } }; -#else -template <> -struct TypeCvtOp : UnaryOpBase, - FixupBase { - constexpr static size_t SIMD_WIDTH = 4; - - TypeCvtOp(DType src_dtype, DType dst_dtype) - : UnaryOpBase(src_dtype, dst_dtype), FixupBase(scale) {} - - TypeCvtOp(float src_scale, float dst_scale) - : UnaryOpBase(src_scale, dst_scale), FixupBase(scale) {} - - void operator()(const int32x4x2_t& vsrc, dt_qint8* dst) const { - vst1_s8(reinterpret_cast(dst), operator()(vsrc)); - } - void operator()(const int32x4_t& vsrc, dt_qint8* dst) const { - vst1_lane_s32(reinterpret_cast(dst), - (int32x2_t)(operator()(vsrc)), 0); - } - dt_qint8 operator()(const dt_qint32& src) const { - float fsrc = src.as_int32() * this->scale; - return QConverter::convert(fsrc); - } - void operator()(const src_ctype& src, dst_ctype* dst) const { - *dst = operator()(src); - } - int8x8_t operator()(const int32x4x2_t& vsrc) const { - int32x4_t vitem0 = vqrdmulhq_s32(vsrc.val[0], vmultiplier); - int32x4_t vitem1 = vqrdmulhq_s32(vsrc.val[1], vmultiplier); - auto fixup0 = vshrq_n_s32(vitem0, 31); - auto fixup1 = vshrq_n_s32(vitem1, 31); - // FIXME Theoretically, we should check shift != 0 here. - vitem0 = vqaddq_s32(vitem0, fixup0); - vitem1 = vqaddq_s32(vitem1, fixup1); - return vqmovn_s16(vcombine_s16(vqmovn_s32(vrshlq_s32(vitem0, vshift)), - vqmovn_s32(vrshlq_s32(vitem1, vshift)))); - } - int8x8_t operator()(const int32x4_t& src) const { - int32x4_t vitem0 = vqrdmulhq_s32(src, vmultiplier); - auto fixup0 = vshrq_n_s32(vitem0, 31); - vitem0 = vqaddq_s32(vitem0, fixup0); - int16x4_t vres0_int16 = vqmovn_s32(vrshlq_s32(vitem0, vshift)); - return vqmovn_s16(vcombine_s16(vres0_int16, vres0_int16)); - } - int8x8_t operator()(const float32x4_t& src) const { - int32x4_t vitem0 = vqrdmulhq_s32(vcvtq_s32_f32(src), vmultiplier); - auto fixup0 = vshrq_n_s32(vitem0, 31); - vitem0 = vqaddq_s32(vitem0, fixup0); - int16x4_t vres0_int16 = vqmovn_s32(vrshlq_s32(vitem0, vshift)); - return vqmovn_s16(vcombine_s16(vres0_int16, vres0_int16)); - } -}; -#endif template <> struct TypeCvtOp : UnaryOpBase { diff --git a/dnn/src/common/nchw_nchwxx_valid.h b/dnn/src/common/nchw_nchwxx_valid.h index e1d0b6f0..7c4621bc 100644 --- a/dnn/src/common/nchw_nchwxx_valid.h +++ b/dnn/src/common/nchw_nchwxx_valid.h @@ -144,7 +144,7 @@ inline bool nchw_nchwxx_valid( const DTypeEnum dst_dtype, const ConvolutionBase::CanonizedFilterMeta& fm, const BiasMode bias_mode, - const param::ConvBias::NonlineMode nonline_mode) { + const param::ConvBias::NonlineMode ) { bool ok_type = ((src_dtype == DTypeEnum::Float32 && filter_dtype == DTypeEnum::Float32 && (dst_dtype == DTypeEnum::Float32))) && diff --git a/src/gopt/test/inference.cpp b/src/gopt/test/inference.cpp index ee8dc0ec..f8ad6450 100644 --- a/src/gopt/test/inference.cpp +++ b/src/gopt/test/inference.cpp @@ -32,7 +32,6 @@ #include "./helper.h" #include "megbrain/comp_node_env.h" -#include "cpuinfo.h" #include "megdnn/tensor_format.h" #include