diff --git a/src/layer/arm/convolution_3x3_pack1to4_fp16s.h b/src/layer/arm/convolution_3x3_pack1to4_fp16s.h new file mode 100644 index 000000000..f8a055cd6 --- /dev/null +++ b/src/layer/arm/convolution_3x3_pack1to4_fp16s.h @@ -0,0 +1,646 @@ +// Tencent is pleased to support the open source community by making ncnn available. +// +// Copyright (C) 2021 THL A29 Limited, a Tencent company. All rights reserved. +// +// Licensed under the BSD 3-Clause License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/licenses/BSD-3-Clause +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +static void conv3x3s1_pack1to4_fp16sa_neon(const Mat& bottom_blob, Mat& top_blob, const Mat& kernel, const Mat& _bias, const Option& opt) +{ + int inch = bottom_blob.c; + int outw = top_blob.w; + int outh = top_blob.h; + int outch = top_blob.c; + + const __fp16* bias = _bias; + + #pragma omp parallel for num_threads(opt.num_threads) + for (int p = 0; p < outch; p++) + { + Mat out0 = top_blob.channel(p); + + float16x4_t _bias0 = bias ? vld1_f16(bias + p * 4) : vdup_n_f16((__fp16)0.f); + out0.fill(_bias0); + + const __fp16* k0 = kernel.channel(p); + + int q = 0; + for (; q < inch; q++) + { + __fp16* outptr0 = out0; + + const Mat img0 = bottom_blob.channel(q); + + const __fp16* r0 = img0.row(0); + const __fp16* r1 = img0.row(1); + const __fp16* r2 = img0.row(2); + + float16x4_t _k00 = vld1_f16(k0); + float16x4_t _k01 = vld1_f16(k0 + 4); + float16x4_t _k02 = vld1_f16(k0 + 8); + float16x4_t _k10 = vld1_f16(k0 + 12); + float16x4_t _k11 = vld1_f16(k0 + 16); + float16x4_t _k12 = vld1_f16(k0 + 20); + float16x4_t _k20 = vld1_f16(k0 + 24); + float16x4_t _k21 = vld1_f16(k0 + 28); + float16x4_t _k22 = vld1_f16(k0 + 32); + + int i = 0; + for (; i < outh; i++) + { + int j = 0; + for (; j + 7 < outw; j += 8) + { + asm volatile( + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [%0], #32 \n" // sum0 sum1 sum2 sum3 + + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0] \n" // sum4 sum5 sum6 sum7 + + "sub %0, %0, #32 \n" + + "prfm pldl1keep, [%1, #128] \n" + "ld1 {v0.8h}, [%1], #16 \n" // r0 + "ld1 {v1.4h}, [%1] \n" + + "fmla v24.4h, %8.4h, v0.h[0] \n" + "fmla v25.4h, %8.4h, v0.h[1] \n" + "fmla v26.4h, %8.4h, v0.h[2] \n" + "fmla v27.4h, %8.4h, v0.h[3] \n" + "fmla v28.4h, %8.4h, v0.h[4] \n" + "fmla v29.4h, %8.4h, v0.h[5] \n" + "fmla v30.4h, %8.4h, v0.h[6] \n" + "fmla v31.4h, %8.4h, v0.h[7] \n" + + "fmla v24.4h, %9.4h, v0.h[1] \n" + "fmla v25.4h, %9.4h, v0.h[2] \n" + "fmla v26.4h, %9.4h, v0.h[3] \n" + "fmla v27.4h, %9.4h, v0.h[4] \n" + "fmla v28.4h, %9.4h, v0.h[5] \n" + "fmla v29.4h, %9.4h, v0.h[6] \n" + "fmla v30.4h, %9.4h, v0.h[7] \n" + "fmla v31.4h, %9.4h, v1.h[0] \n" + + "fmla v24.4h, %10.4h, v0.h[2] \n" + "fmla v25.4h, %10.4h, v0.h[3] \n" + "fmla v26.4h, %10.4h, v0.h[4] \n" + "fmla v27.4h, %10.4h, v0.h[5] \n" + "fmla v28.4h, %10.4h, v0.h[6] \n" + "fmla v29.4h, %10.4h, v0.h[7] \n" + "fmla v30.4h, %10.4h, v1.h[0] \n" + "fmla v31.4h, %10.4h, v1.h[1] \n" + + "prfm pldl1keep, [%2, #128] \n" + "ld1 {v2.8h}, [%2], #16 \n" // r1 + "ld1 {v3.4h}, [%2] \n" + + "fmla v24.4h, %11.4h, v2.h[0] \n" + "fmla v25.4h, %11.4h, v2.h[1] \n" + "fmla v26.4h, %11.4h, v2.h[2] \n" + "fmla v27.4h, %11.4h, v2.h[3] \n" + "fmla v28.4h, %11.4h, v2.h[4] \n" + "fmla v29.4h, %11.4h, v2.h[5] \n" + "fmla v30.4h, %11.4h, v2.h[6] \n" + "fmla v31.4h, %11.4h, v2.h[7] \n" + + "fmla v24.4h, %12.4h, v2.h[1] \n" + "fmla v25.4h, %12.4h, v2.h[2] \n" + "fmla v26.4h, %12.4h, v2.h[3] \n" + "fmla v27.4h, %12.4h, v2.h[4] \n" + "fmla v28.4h, %12.4h, v2.h[5] \n" + "fmla v29.4h, %12.4h, v2.h[6] \n" + "fmla v30.4h, %12.4h, v2.h[7] \n" + "fmla v31.4h, %12.4h, v3.h[0] \n" + + "fmla v24.4h, %13.4h, v2.h[2] \n" + "fmla v25.4h, %13.4h, v2.h[3] \n" + "fmla v26.4h, %13.4h, v2.h[4] \n" + "fmla v27.4h, %13.4h, v2.h[5] \n" + "fmla v28.4h, %13.4h, v2.h[6] \n" + "fmla v29.4h, %13.4h, v2.h[7] \n" + "fmla v30.4h, %13.4h, v3.h[0] \n" + "fmla v31.4h, %13.4h, v3.h[1] \n" + + "prfm pldl1keep, [%3, #128] \n" + "ld1 {v4.8h}, [%3], #16 \n" // r2 + "ld1 {v5.4h}, [%3] \n" + + "fmla v24.4h, %14.4h, v4.h[0] \n" + "fmla v25.4h, %14.4h, v4.h[1] \n" + "fmla v26.4h, %14.4h, v4.h[2] \n" + "fmla v27.4h, %14.4h, v4.h[3] \n" + "fmla v28.4h, %14.4h, v4.h[4] \n" + "fmla v29.4h, %14.4h, v4.h[5] \n" + "fmla v30.4h, %14.4h, v4.h[6] \n" + "fmla v31.4h, %14.4h, v4.h[7] \n" + + "fmla v24.4h, %15.4h, v4.h[1] \n" + "fmla v25.4h, %15.4h, v4.h[2] \n" + "fmla v26.4h, %15.4h, v4.h[3] \n" + "fmla v27.4h, %15.4h, v4.h[4] \n" + "fmla v28.4h, %15.4h, v4.h[5] \n" + "fmla v29.4h, %15.4h, v4.h[6] \n" + "fmla v30.4h, %15.4h, v4.h[7] \n" + "fmla v31.4h, %15.4h, v5.h[0] \n" + + "fmla v24.4h, %16.4h, v4.h[2] \n" + "fmla v25.4h, %16.4h, v4.h[3] \n" + "fmla v26.4h, %16.4h, v4.h[4] \n" + "fmla v27.4h, %16.4h, v4.h[5] \n" + "fmla v28.4h, %16.4h, v4.h[6] \n" + "fmla v29.4h, %16.4h, v4.h[7] \n" + "fmla v30.4h, %16.4h, v5.h[0] \n" + "fmla v31.4h, %16.4h, v5.h[1] \n" + + "st1 {v24.4h, v25.4h, v26.4h, v27.4h}, [%0], #32 \n" + "st1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0], #32 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); + } + for (; j + 3 < outw; j += 4) + { + asm volatile( + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0] \n" // sum0 sum1 sum2 sum3 + + "prfm pldl1keep, [%1, #128] \n" + "ld1 {v0.8h}, [%1] \n" // r0 + + "fmla v28.4h, %8.4h, v0.h[0] \n" + "fmla v29.4h, %8.4h, v0.h[1] \n" + "fmla v30.4h, %8.4h, v0.h[2] \n" + "fmla v31.4h, %8.4h, v0.h[3] \n" + + "fmla v28.4h, %9.4h, v0.h[1] \n" + "fmla v29.4h, %9.4h, v0.h[2] \n" + "fmla v30.4h, %9.4h, v0.h[3] \n" + "fmla v31.4h, %9.4h, v0.h[4] \n" + + "fmla v28.4h, %10.4h, v0.h[2] \n" + "fmla v29.4h, %10.4h, v0.h[3] \n" + "fmla v30.4h, %10.4h, v0.h[4] \n" + "fmla v31.4h, %10.4h, v0.h[5] \n" + + "prfm pldl1keep, [%2, #128] \n" + "ld1 {v1.8h}, [%2] \n" // r1 + + "fmla v28.4h, %11.4h, v1.h[0] \n" + "fmla v29.4h, %11.4h, v1.h[1] \n" + "fmla v30.4h, %11.4h, v1.h[2] \n" + "fmla v31.4h, %11.4h, v1.h[3] \n" + + "fmla v28.4h, %12.4h, v1.h[1] \n" + "fmla v29.4h, %12.4h, v1.h[2] \n" + "fmla v30.4h, %12.4h, v1.h[3] \n" + "fmla v31.4h, %12.4h, v1.h[4] \n" + + "fmla v28.4h, %13.4h, v1.h[2] \n" + "fmla v29.4h, %13.4h, v1.h[3] \n" + "fmla v30.4h, %13.4h, v1.h[4] \n" + "fmla v31.4h, %13.4h, v1.h[5] \n" + + "prfm pldl1keep, [%3, #128] \n" + "ld1 {v2.8h}, [%3] \n" // r2 + + "fmla v28.4h, %14.4h, v2.h[0] \n" + "fmla v29.4h, %14.4h, v2.h[1] \n" + "fmla v30.4h, %14.4h, v2.h[2] \n" + "fmla v31.4h, %14.4h, v2.h[3] \n" + + "fmla v28.4h, %15.4h, v2.h[1] \n" + "fmla v29.4h, %15.4h, v2.h[2] \n" + "fmla v30.4h, %15.4h, v2.h[3] \n" + "fmla v31.4h, %15.4h, v2.h[4] \n" + + "fmla v28.4h, %16.4h, v2.h[2] \n" + "fmla v29.4h, %16.4h, v2.h[3] \n" + "fmla v30.4h, %16.4h, v2.h[4] \n" + "fmla v31.4h, %16.4h, v2.h[5] \n" + + "add %1, %1, #8 \n" + "add %2, %2, #8 \n" + "add %3, %3, #8 \n" + + "st1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0], #32 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v28", "v29", "v30", "v31"); + } + for (; j + 1 < outw; j += 2) + { + asm volatile( + "prfm pldl1keep, [%0, #128] \n" + "ld1 {v30.4h, v31.4h}, [%0] \n" // sum0 sum1 + + "prfm pldl1keep, [%1, #64] \n" + "ld1 {v0.4h}, [%1] \n" // r0 + + "fmla v30.4h, %8.4h, v0.h[0] \n" + "fmla v31.4h, %8.4h, v0.h[1] \n" + "fmla v30.4h, %9.4h, v0.h[1] \n" + "fmla v31.4h, %9.4h, v0.h[2] \n" + "fmla v30.4h, %10.4h, v0.h[2] \n" + "fmla v31.4h, %10.4h, v0.h[3] \n" + + "prfm pldl1keep, [%2, #64] \n" + "ld1 {v1.4h}, [%2] \n" // r1 + + "fmla v30.4h, %11.4h, v1.h[0] \n" + "fmla v31.4h, %11.4h, v1.h[1] \n" + "fmla v30.4h, %12.4h, v1.h[1] \n" + "fmla v31.4h, %12.4h, v1.h[2] \n" + "fmla v30.4h, %13.4h, v1.h[2] \n" + "fmla v31.4h, %13.4h, v1.h[3] \n" + + "prfm pldl1keep, [%3, #64] \n" + "ld1 {v2.4h}, [%3] \n" // r2 + + "fmla v30.4h, %14.4h, v2.h[0] \n" + "fmla v31.4h, %14.4h, v2.h[1] \n" + "fmla v30.4h, %15.4h, v2.h[1] \n" + "fmla v31.4h, %15.4h, v2.h[2] \n" + "fmla v30.4h, %16.4h, v2.h[2] \n" + "fmla v31.4h, %16.4h, v2.h[3] \n" + + "add %1, %1, #4 \n" + "add %2, %2, #4 \n" + "add %3, %3, #4 \n" + + "st1 {v30.4h, v31.4h}, [%0], #16 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v30", "v31"); + } + for (; j < outw; j++) + { + asm volatile( + "prfm pldl1keep, [%0, #64] \n" + "ld1 {v30.4h}, [%0] \n" // sum0 + + "prfm pldl1keep, [%1, #64] \n" + "ld1 {v0.4h}, [%1] \n" // r0 + + "fmla v30.4h, %8.4h, v0.h[0] \n" + "fmla v30.4h, %9.4h, v0.h[1] \n" + "fmla v30.4h, %10.4h, v0.h[2] \n" + + "prfm pldl1keep, [%2, #64] \n" + "ld1 {v1.4h}, [%2] \n" // r1 + + "fmla v30.4h, %11.4h, v1.h[0] \n" + "fmla v30.4h, %12.4h, v1.h[1] \n" + "fmla v30.4h, %13.4h, v1.h[2] \n" + + "prfm pldl1keep, [%3, #64] \n" + "ld1 {v2.4h}, [%3] \n" // r2 + + "fmla v30.4h, %14.4h, v2.h[0] \n" + "fmla v30.4h, %15.4h, v2.h[1] \n" + "fmla v30.4h, %16.4h, v2.h[2] \n" + + "add %1, %1, #2 \n" + "add %2, %2, #2 \n" + "add %3, %3, #2 \n" + + "st1 {v30.4h}, [%0], #8 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v30"); + } + + r0 += 2; + r1 += 2; + r2 += 2; + } + + k0 += 9 * 4; + } + } +} + +static void conv3x3s2_pack1to4_fp16sa_neon(const Mat& bottom_blob, Mat& top_blob, const Mat& kernel, const Mat& _bias, const Option& opt) +{ + int w = bottom_blob.w; + int inch = bottom_blob.c; + int outw = top_blob.w; + int outh = top_blob.h; + int outch = top_blob.c; + + const int tailstep = w - 2 * outw + w; + + const __fp16* bias = _bias; + + #pragma omp parallel for num_threads(opt.num_threads) + for (int p = 0; p < outch; p++) + { + Mat out0 = top_blob.channel(p); + + float16x4_t _bias0 = bias ? vld1_f16(bias + p * 4) : vdup_n_f16((__fp16)0.f); + out0.fill(_bias0); + + const __fp16* k0 = kernel.channel(p); + + int q = 0; + for (; q < inch; q++) + { + __fp16* outptr0 = out0; + + const Mat img0 = bottom_blob.channel(q); + + const __fp16* r0 = img0.row(0); + const __fp16* r1 = img0.row(1); + const __fp16* r2 = img0.row(2); + + float16x4_t _k00 = vld1_f16(k0); + float16x4_t _k01 = vld1_f16(k0 + 4); + float16x4_t _k02 = vld1_f16(k0 + 8); + float16x4_t _k10 = vld1_f16(k0 + 12); + float16x4_t _k11 = vld1_f16(k0 + 16); + float16x4_t _k12 = vld1_f16(k0 + 20); + float16x4_t _k20 = vld1_f16(k0 + 24); + float16x4_t _k21 = vld1_f16(k0 + 28); + float16x4_t _k22 = vld1_f16(k0 + 32); + + int i = 0; + for (; i < outh; i++) + { + int j = 0; + for (; j + 3 < outw; j += 4) + { + asm volatile( + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0] \n" // sum0 sum1 sum2 sum3 + + "prfm pldl1keep, [%1, #128] \n" + "ld1 {v0.8h}, [%1], #16 \n" // r0 + "ld1 {v1.h}[0], [%1] \n" + + "fmla v28.4h, %8.4h, v0.h[0] \n" + "fmla v29.4h, %8.4h, v0.h[2] \n" + "fmla v30.4h, %8.4h, v0.h[4] \n" + "fmla v31.4h, %8.4h, v0.h[6] \n" + + "fmla v28.4h, %9.4h, v0.h[1] \n" + "fmla v29.4h, %9.4h, v0.h[3] \n" + "fmla v30.4h, %9.4h, v0.h[5] \n" + "fmla v31.4h, %9.4h, v0.h[7] \n" + + "fmla v28.4h, %10.4h, v0.h[2] \n" + "fmla v29.4h, %10.4h, v0.h[4] \n" + "fmla v30.4h, %10.4h, v0.h[6] \n" + "fmla v31.4h, %10.4h, v1.h[0] \n" + + "prfm pldl1keep, [%2, #128] \n" + "ld1 {v2.8h}, [%2], #16 \n" // r1 + "ld1 {v3.h}[0], [%2] \n" + + "fmla v28.4h, %11.4h, v2.h[0] \n" + "fmla v29.4h, %11.4h, v2.h[2] \n" + "fmla v30.4h, %11.4h, v2.h[4] \n" + "fmla v31.4h, %11.4h, v2.h[6] \n" + + "fmla v28.4h, %12.4h, v2.h[1] \n" + "fmla v29.4h, %12.4h, v2.h[3] \n" + "fmla v30.4h, %12.4h, v2.h[5] \n" + "fmla v31.4h, %12.4h, v2.h[7] \n" + + "fmla v28.4h, %13.4h, v2.h[2] \n" + "fmla v29.4h, %13.4h, v2.h[4] \n" + "fmla v30.4h, %13.4h, v2.h[6] \n" + "fmla v31.4h, %13.4h, v3.h[0] \n" + + "prfm pldl1keep, [%3, #128] \n" + "ld1 {v4.8h}, [%3], #16 \n" // r2 + "ld1 {v5.h}[0], [%3] \n" + + "fmla v28.4h, %14.4h, v4.h[0] \n" + "fmla v29.4h, %14.4h, v4.h[2] \n" + "fmla v30.4h, %14.4h, v4.h[4] \n" + "fmla v31.4h, %14.4h, v4.h[6] \n" + + "fmla v28.4h, %15.4h, v4.h[1] \n" + "fmla v29.4h, %15.4h, v4.h[3] \n" + "fmla v30.4h, %15.4h, v4.h[5] \n" + "fmla v31.4h, %15.4h, v4.h[7] \n" + + "fmla v28.4h, %16.4h, v4.h[2] \n" + "fmla v29.4h, %16.4h, v4.h[4] \n" + "fmla v30.4h, %16.4h, v4.h[6] \n" + "fmla v31.4h, %16.4h, v5.h[0] \n" + + "st1 {v28.4h, v29.4h, v30.4h, v31.4h}, [%0], #32 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v28", "v29", "v30", "v31"); + } + for (; j + 1 < outw; j += 2) + { + asm volatile( + "prfm pldl1keep, [%0, #128] \n" + "ld1 {v30.4h, v31.4h}, [%0] \n" // sum0 sum1 + + "prfm pldl1keep, [%1, #64] \n" + "ld1 {v0.4h}, [%1], #8 \n" // r0 + "ld1 {v1.h}[0], [%1] \n" + + "fmla v30.4h, %8.4h, v0.h[0] \n" + "fmla v31.4h, %8.4h, v0.h[2] \n" + "fmla v30.4h, %9.4h, v0.h[1] \n" + "fmla v31.4h, %9.4h, v0.h[3] \n" + "fmla v30.4h, %10.4h, v0.h[2] \n" + "fmla v31.4h, %10.4h, v1.h[0] \n" + + "prfm pldl1keep, [%2, #64] \n" + "ld1 {v2.4h}, [%2], #8 \n" // r1 + "ld1 {v3.h}[0], [%2] \n" + + "fmla v30.4h, %11.4h, v2.h[0] \n" + "fmla v31.4h, %11.4h, v2.h[2] \n" + "fmla v30.4h, %12.4h, v2.h[1] \n" + "fmla v31.4h, %12.4h, v2.h[3] \n" + "fmla v30.4h, %13.4h, v2.h[2] \n" + "fmla v31.4h, %13.4h, v3.h[0] \n" + + "prfm pldl1keep, [%3, #64] \n" + "ld1 {v4.4h}, [%3], #8 \n" // r2 + "ld1 {v5.h}[0], [%3] \n" + + "fmla v30.4h, %14.4h, v4.h[0] \n" + "fmla v31.4h, %14.4h, v4.h[2] \n" + "fmla v30.4h, %15.4h, v4.h[1] \n" + "fmla v31.4h, %15.4h, v4.h[3] \n" + "fmla v30.4h, %16.4h, v4.h[2] \n" + "fmla v31.4h, %16.4h, v5.h[0] \n" + + "st1 {v30.4h, v31.4h}, [%0], #16 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v30", "v31"); + } + for (; j < outw; j++) + { + asm volatile( + "prfm pldl1keep, [%0, #64] \n" + "ld1 {v30.4h}, [%0] \n" // sum0 + + "prfm pldl1keep, [%1, #64] \n" + "ld1 {v0.4h}, [%1] \n" // r0 + + "fmla v30.4h, %8.4h, v0.h[0] \n" + "fmla v30.4h, %9.4h, v0.h[1] \n" + "fmla v30.4h, %10.4h, v0.h[2] \n" + + "prfm pldl1keep, [%2, #64] \n" + "ld1 {v1.4h}, [%2] \n" // r1 + + "fmla v30.4h, %11.4h, v1.h[0] \n" + "fmla v30.4h, %12.4h, v1.h[1] \n" + "fmla v30.4h, %13.4h, v1.h[2] \n" + + "prfm pldl1keep, [%3, #64] \n" + "ld1 {v2.4h}, [%3] \n" // r2 + + "fmla v30.4h, %14.4h, v2.h[0] \n" + "fmla v30.4h, %15.4h, v2.h[1] \n" + "fmla v30.4h, %16.4h, v2.h[2] \n" + + "add %1, %1, #4 \n" + "add %2, %2, #4 \n" + "add %3, %3, #4 \n" + + "st1 {v30.4h}, [%0], #8 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00), // %8 + "w"(_k01), // %9 + "w"(_k02), // %10 + "w"(_k10), // %11 + "w"(_k11), // %12 + "w"(_k12), // %13 + "w"(_k20), // %14 + "w"(_k21), // %15 + "w"(_k22) // %16 + : "cc", "memory", "v0", "v1", "v2", "v30"); + } + + r0 += tailstep; + r1 += tailstep; + r2 += tailstep; + } + + k0 += 9 * 4; + } + } +} diff --git a/src/layer/arm/convolution_3x3_pack4_fp16s.h b/src/layer/arm/convolution_3x3_pack4_fp16s.h index 78fa1dc88..2b221c12f 100644 --- a/src/layer/arm/convolution_3x3_pack4_fp16s.h +++ b/src/layer/arm/convolution_3x3_pack4_fp16s.h @@ -1152,3 +1152,565 @@ static void conv3x3s1_winograd64_pack4_fp16sa_neon(const Mat& bottom_blob, Mat& // cut result pad copy_cut_border(top_blob_bordered, top_blob, 0, top_blob_bordered.h - top_blob.h, 0, top_blob_bordered.w - top_blob.w, opt); } + +static void conv3x3s1_pack4_fp16sa_neon(const Mat& bottom_blob, Mat& top_blob, const Mat& kernel, const Mat& _bias, const Option& opt) +{ + int w = bottom_blob.w; + int inch = bottom_blob.c; + int outw = top_blob.w; + int outh = top_blob.h; + int outch = top_blob.c; + + const __fp16* bias = _bias; + + #pragma omp parallel for num_threads(opt.num_threads) + for (int p = 0; p < outch; p++) + { + Mat out0 = top_blob.channel(p); + + float16x4_t _bias0 = bias ? vld1_f16(bias + p * 4) : vdup_n_f16((__fp16)0.f); + out0.fill(_bias0); + + int q = 0; + for (; q < inch; q++) + { + __fp16* outptr0 = out0.row<__fp16>(0); + + const Mat img0 = bottom_blob.channel(q); + + const __fp16* r0 = img0.row(0); + const __fp16* r1 = img0.row(1); + const __fp16* r2 = img0.row(2); + + const __fp16* kptr = kernel.channel(p).row(q); + + // 16 * 9 + float16x8_t _k00_01 = vld1q_f16(kptr); + float16x8_t _k00_23 = vld1q_f16(kptr + 8); + float16x8_t _k01_01 = vld1q_f16(kptr + 16); + float16x8_t _k01_23 = vld1q_f16(kptr + 24); + float16x8_t _k02_01 = vld1q_f16(kptr + 32); + float16x8_t _k02_23 = vld1q_f16(kptr + 40); + float16x8_t _k10_01 = vld1q_f16(kptr + 48); + float16x8_t _k10_23 = vld1q_f16(kptr + 56); + float16x8_t _k11_01 = vld1q_f16(kptr + 64); + float16x8_t _k11_23 = vld1q_f16(kptr + 72); + float16x8_t _k12_01 = vld1q_f16(kptr + 80); + float16x8_t _k12_23 = vld1q_f16(kptr + 88); + float16x8_t _k20_01 = vld1q_f16(kptr + 96); + float16x8_t _k20_23 = vld1q_f16(kptr + 104); + float16x8_t _k21_01 = vld1q_f16(kptr + 112); + float16x8_t _k21_23 = vld1q_f16(kptr + 120); + float16x8_t _k22_01 = vld1q_f16(kptr + 128); + float16x8_t _k22_23 = vld1q_f16(kptr + 136); + + int i = 0; + for (; i < outh; i++) + { + int j = 0; + for (; j + 3 < outw; j += 4) + { + asm volatile( + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v10.4h, v11.4h, v12.4h, v13.4h}, [%0] \n" // sum0 sum1 sum2 sum3 + + "prfm pldl1keep, [%1, #384] \n" + "ld1 {v0.8h, v1.8h, v2.8h}, [%1] \n" // r00 r01 r02 r03 r04 r05 + + "ext v6.16b, %8.16b, %8.16b, #8 \n" + "fmla v10.4h, %8.4h, v0.h[0] \n" + "fmla v11.4h, %8.4h, v0.h[4] \n" + "fmla v12.4h, %8.4h, v1.h[0] \n" + "fmla v13.4h, %8.4h, v1.h[4] \n" + "fmla v10.4h, v6.4h, v0.h[1] \n" + "fmla v11.4h, v6.4h, v0.h[5] \n" + "fmla v12.4h, v6.4h, v1.h[1] \n" + "fmla v13.4h, v6.4h, v1.h[5] \n" + "ext v7.16b, %9.16b, %9.16b, #8 \n" + "fmla v10.4h, %9.4h, v0.h[2] \n" + "fmla v11.4h, %9.4h, v0.h[6] \n" + "fmla v12.4h, %9.4h, v1.h[2] \n" + "fmla v13.4h, %9.4h, v1.h[6] \n" + "fmla v10.4h, v7.4h, v0.h[3] \n" + "fmla v11.4h, v7.4h, v0.h[7] \n" + "fmla v12.4h, v7.4h, v1.h[3] \n" + "fmla v13.4h, v7.4h, v1.h[7] \n" + + "ext v8.16b, %10.16b, %10.16b, #8 \n" + "fmla v10.4h, %10.4h, v0.h[4] \n" + "fmla v11.4h, %10.4h, v1.h[0] \n" + "fmla v12.4h, %10.4h, v1.h[4] \n" + "fmla v13.4h, %10.4h, v2.h[0] \n" + "fmla v10.4h, v8.4h, v0.h[5] \n" + "fmla v11.4h, v8.4h, v1.h[1] \n" + "fmla v12.4h, v8.4h, v1.h[5] \n" + "fmla v13.4h, v8.4h, v2.h[1] \n" + "ext v9.16b, %11.16b, %11.16b, #8 \n" + "fmla v10.4h, %11.4h, v0.h[6] \n" + "fmla v11.4h, %11.4h, v1.h[2] \n" + "fmla v12.4h, %11.4h, v1.h[6] \n" + "fmla v13.4h, %11.4h, v2.h[2] \n" + "fmla v10.4h, v9.4h, v0.h[7] \n" + "fmla v11.4h, v9.4h, v1.h[3] \n" + "fmla v12.4h, v9.4h, v1.h[7] \n" + "fmla v13.4h, v9.4h, v2.h[3] \n" + + "prfm pldl1keep, [%2, #384] \n" + "ld1 {v3.8h, v4.8h, v5.8h}, [%2] \n" // r10 r11 r12 r13 r14 r15 + + "ext v6.16b, %12.16b, %12.16b, #8 \n" + "fmla v10.4h, %12.4h, v1.h[0] \n" + "fmla v11.4h, %12.4h, v1.h[4] \n" + "fmla v12.4h, %12.4h, v2.h[0] \n" + "fmla v13.4h, %12.4h, v2.h[4] \n" + "fmla v10.4h, v6.4h, v1.h[1] \n" + "fmla v11.4h, v6.4h, v1.h[5] \n" + "fmla v12.4h, v6.4h, v2.h[1] \n" + "fmla v13.4h, v6.4h, v2.h[5] \n" + "ext v7.16b, %13.16b, %13.16b, #8 \n" + "fmla v10.4h, %13.4h, v1.h[2] \n" + "fmla v11.4h, %13.4h, v1.h[6] \n" + "fmla v12.4h, %13.4h, v2.h[2] \n" + "fmla v13.4h, %13.4h, v2.h[6] \n" + "fmla v10.4h, v7.4h, v1.h[3] \n" + "fmla v11.4h, v7.4h, v1.h[7] \n" + "fmla v12.4h, v7.4h, v2.h[3] \n" + "fmla v13.4h, v7.4h, v2.h[7] \n" + + "ext v8.16b, %14.16b, %14.16b, #8 \n" + "fmla v10.4h, %14.4h, v3.h[0] \n" + "fmla v11.4h, %14.4h, v3.h[4] \n" + "fmla v12.4h, %14.4h, v4.h[0] \n" + "fmla v13.4h, %14.4h, v4.h[4] \n" + "fmla v10.4h, v8.4h, v3.h[1] \n" + "fmla v11.4h, v8.4h, v3.h[5] \n" + "fmla v12.4h, v8.4h, v4.h[1] \n" + "fmla v13.4h, v8.4h, v4.h[5] \n" + "ext v9.16b, %15.16b, %15.16b, #8 \n" + "fmla v10.4h, %15.4h, v3.h[2] \n" + "fmla v11.4h, %15.4h, v3.h[6] \n" + "fmla v12.4h, %15.4h, v4.h[2] \n" + "fmla v13.4h, %15.4h, v4.h[6] \n" + "fmla v10.4h, v9.4h, v3.h[3] \n" + "fmla v11.4h, v9.4h, v3.h[7] \n" + "fmla v12.4h, v9.4h, v4.h[3] \n" + "fmla v13.4h, v9.4h, v4.h[7] \n" + + "ext v6.16b, %16.16b, %16.16b, #8 \n" + "fmla v10.4h, %16.4h, v3.h[4] \n" + "fmla v11.4h, %16.4h, v4.h[0] \n" + "fmla v12.4h, %16.4h, v4.h[4] \n" + "fmla v13.4h, %16.4h, v5.h[0] \n" + "fmla v10.4h, v6.4h, v3.h[5] \n" + "fmla v11.4h, v6.4h, v4.h[1] \n" + "fmla v12.4h, v6.4h, v4.h[5] \n" + "fmla v13.4h, v6.4h, v5.h[1] \n" + "ext v7.16b, %17.16b, %17.16b, #8 \n" + "fmla v10.4h, %17.4h, v3.h[6] \n" + "fmla v11.4h, %17.4h, v4.h[2] \n" + "fmla v12.4h, %17.4h, v4.h[6] \n" + "fmla v13.4h, %17.4h, v5.h[2] \n" + "fmla v10.4h, v7.4h, v3.h[7] \n" + "fmla v11.4h, v7.4h, v4.h[3] \n" + "fmla v12.4h, v7.4h, v4.h[7] \n" + "fmla v13.4h, v7.4h, v5.h[3] \n" + + "prfm pldl1keep, [%3, #384] \n" + "ld1 {v0.8h, v1.8h, v2.8h}, [%3] \n" // r20 r21 r22 r23 r24 r25 + + "ext v8.16b, %18.16b, %18.16b, #8 \n" + "fmla v10.4h, %18.4h, v4.h[0] \n" + "fmla v11.4h, %18.4h, v4.h[4] \n" + "fmla v12.4h, %18.4h, v5.h[0] \n" + "fmla v13.4h, %18.4h, v5.h[4] \n" + "fmla v10.4h, v8.4h, v4.h[1] \n" + "fmla v11.4h, v8.4h, v4.h[5] \n" + "fmla v12.4h, v8.4h, v5.h[1] \n" + "fmla v13.4h, v8.4h, v5.h[5] \n" + "ext v9.16b, %19.16b, %19.16b, #8 \n" + "fmla v10.4h, %19.4h, v4.h[2] \n" + "fmla v11.4h, %19.4h, v4.h[6] \n" + "fmla v12.4h, %19.4h, v5.h[2] \n" + "fmla v13.4h, %19.4h, v5.h[6] \n" + "fmla v10.4h, v9.4h, v4.h[3] \n" + "fmla v11.4h, v9.4h, v4.h[7] \n" + "fmla v12.4h, v9.4h, v5.h[3] \n" + "fmla v13.4h, v9.4h, v5.h[7] \n" + + "ext v6.16b, %20.16b, %20.16b, #8 \n" + "fmla v10.4h, %20.4h, v0.h[0] \n" + "fmla v11.4h, %20.4h, v0.h[4] \n" + "fmla v12.4h, %20.4h, v1.h[0] \n" + "fmla v13.4h, %20.4h, v1.h[4] \n" + "fmla v10.4h, v6.4h, v0.h[1] \n" + "fmla v11.4h, v6.4h, v0.h[5] \n" + "fmla v12.4h, v6.4h, v1.h[1] \n" + "fmla v13.4h, v6.4h, v1.h[5] \n" + "ext v7.16b, %21.16b, %21.16b, #8 \n" + "fmla v10.4h, %21.4h, v0.h[2] \n" + "fmla v11.4h, %21.4h, v0.h[6] \n" + "fmla v12.4h, %21.4h, v1.h[2] \n" + "fmla v13.4h, %21.4h, v1.h[6] \n" + "fmla v10.4h, v7.4h, v0.h[3] \n" + "fmla v11.4h, v7.4h, v0.h[7] \n" + "fmla v12.4h, v7.4h, v1.h[3] \n" + "fmla v13.4h, v7.4h, v1.h[7] \n" + + "ext v8.16b, %22.16b, %22.16b, #8 \n" + "fmla v10.4h, %22.4h, v0.h[4] \n" + "fmla v11.4h, %22.4h, v1.h[0] \n" + "fmla v12.4h, %22.4h, v1.h[4] \n" + "fmla v13.4h, %22.4h, v2.h[0] \n" + "fmla v10.4h, v8.4h, v0.h[5] \n" + "fmla v11.4h, v8.4h, v1.h[1] \n" + "fmla v12.4h, v8.4h, v1.h[5] \n" + "fmla v13.4h, v8.4h, v2.h[1] \n" + "ext v9.16b, %23.16b, %23.16b, #8 \n" + "fmla v10.4h, %23.4h, v0.h[6] \n" + "fmla v11.4h, %23.4h, v1.h[2] \n" + "fmla v12.4h, %23.4h, v1.h[6] \n" + "fmla v13.4h, %23.4h, v2.h[2] \n" + "fmla v10.4h, v9.4h, v0.h[7] \n" + "fmla v11.4h, v9.4h, v1.h[3] \n" + "fmla v12.4h, v9.4h, v1.h[7] \n" + "fmla v13.4h, v9.4h, v2.h[3] \n" + + "ext v6.16b, %24.16b, %24.16b, #8 \n" + "fmla v10.4h, %24.4h, v1.h[0] \n" + "fmla v11.4h, %24.4h, v1.h[4] \n" + "fmla v12.4h, %24.4h, v2.h[0] \n" + "fmla v13.4h, %24.4h, v2.h[4] \n" + + "add %1, %1, #32 \n" + + "fmla v10.4h, v6.4h, v1.h[1] \n" + "fmla v11.4h, v6.4h, v1.h[5] \n" + "fmla v12.4h, v6.4h, v2.h[1] \n" + "fmla v13.4h, v6.4h, v2.h[5] \n" + "ext v7.16b, %25.16b, %25.16b, #8 \n" + "fmla v10.4h, %25.4h, v1.h[2] \n" + "fmla v11.4h, %25.4h, v1.h[6] \n" + "fmla v12.4h, %25.4h, v2.h[2] \n" + "fmla v13.4h, %25.4h, v2.h[6] \n" + + "add %2, %2, #32 \n" + + "fmla v10.4h, v7.4h, v1.h[3] \n" + "fmla v11.4h, v7.4h, v1.h[7] \n" + "fmla v12.4h, v7.4h, v2.h[3] \n" + "fmla v13.4h, v7.4h, v2.h[7] \n" + + "add %3, %3, #32 \n" + + "st1 {v10.4h, v11.4h, v12.4h, v13.4h}, [%0], #32 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00_01), // %8 + "w"(_k00_23), // %9 + "w"(_k01_01), // %10 + "w"(_k01_23), // %11 + "w"(_k02_01), // %12 + "w"(_k02_23), // %13 + "w"(_k10_01), // %14 + "w"(_k10_23), // %15 + "w"(_k11_01), // %16 + "w"(_k11_23), // %17 + "w"(_k12_01), // %18 + "w"(_k12_23), // %19 + "w"(_k20_01), // %20 + "w"(_k20_23), // %21 + "w"(_k21_01), // %22 + "w"(_k21_23), // %23 + "w"(_k22_01), // %24 + "w"(_k22_23) // %25 + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13"); + } + for (; j + 1 < outw; j += 2) + { + asm volatile( + "prfm pldl1keep, [%1, #256] \n" + "ld1 {v0.8h, v1.8h}, [%1] \n" // r00 r01 r02 r03 + + "prfm pldl1keep, [%0, #128] \n" + "ld1 {v12.4h, v13.4h}, [%0] \n" // sum0 sum1 + + "ext v4.16b, %8.16b, %8.16b, #8 \n" + "fmul v10.4h, %8.4h, v0.h[0] \n" + "fmul v11.4h, %8.4h, v0.h[4] \n" + "fmla v12.4h, v4.4h, v0.h[1] \n" + "fmla v13.4h, v4.4h, v0.h[5] \n" + "ext v5.16b, %9.16b, %9.16b, #8 \n" + "fmla v10.4h, %9.4h, v0.h[2] \n" + "fmla v11.4h, %9.4h, v0.h[6] \n" + "fmla v12.4h, v5.4h, v0.h[3] \n" + "fmla v13.4h, v5.4h, v0.h[7] \n" + + "ext v6.16b, %10.16b, %10.16b, #8 \n" + "fmla v10.4h, %10.4h, v0.h[4] \n" + "fmla v11.4h, %10.4h, v1.h[0] \n" + "fmla v12.4h, v6.4h, v0.h[5] \n" + "fmla v13.4h, v6.4h, v1.h[1] \n" + "ext v7.16b, %11.16b, %11.16b, #8 \n" + "fmla v10.4h, %11.4h, v0.h[6] \n" + "fmla v11.4h, %11.4h, v1.h[2] \n" + "fmla v12.4h, v7.4h, v0.h[7] \n" + "fmla v13.4h, v7.4h, v1.h[3] \n" + + "prfm pldl1keep, [%2, #256] \n" + "ld1 {v2.8h, v3.8h}, [%2] \n" // r10 r11 r12 r13 + + "ext v8.16b, %12.16b, %12.16b, #8 \n" + "fmla v10.4h, %12.4h, v1.h[0] \n" + "fmla v11.4h, %12.4h, v1.h[4] \n" + "fmla v12.4h, v8.4h, v1.h[1] \n" + "fmla v13.4h, v8.4h, v1.h[5] \n" + "ext v9.16b, %13.16b, %13.16b, #8 \n" + "fmla v10.4h, %13.4h, v1.h[2] \n" + "fmla v11.4h, %13.4h, v1.h[6] \n" + "fmla v12.4h, v9.4h, v1.h[3] \n" + "fmla v13.4h, v9.4h, v1.h[7] \n" + + "ext v4.16b, %14.16b, %14.16b, #8 \n" + "fmla v10.4h, %14.4h, v2.h[0] \n" + "fmla v11.4h, %14.4h, v2.h[4] \n" + "fmla v12.4h, v4.4h, v2.h[1] \n" + "fmla v13.4h, v4.4h, v2.h[5] \n" + "ext v5.16b, %15.16b, %15.16b, #8 \n" + "fmla v10.4h, %15.4h, v2.h[2] \n" + "fmla v11.4h, %15.4h, v2.h[6] \n" + "fmla v12.4h, v5.4h, v2.h[3] \n" + "fmla v13.4h, v5.4h, v2.h[7] \n" + + "ext v6.16b, %16.16b, %16.16b, #8 \n" + "fmla v10.4h, %16.4h, v2.h[4] \n" + "fmla v11.4h, %16.4h, v3.h[0] \n" + "fmla v12.4h, v6.4h, v2.h[5] \n" + "fmla v13.4h, v6.4h, v3.h[1] \n" + "ext v7.16b, %17.16b, %17.16b, #8 \n" + "fmla v10.4h, %17.4h, v2.h[6] \n" + "fmla v11.4h, %17.4h, v3.h[2] \n" + "fmla v12.4h, v7.4h, v2.h[7] \n" + "fmla v13.4h, v7.4h, v3.h[3] \n" + + "prfm pldl1keep, [%3, #256] \n" + "ld1 {v0.8h, v1.8h}, [%3] \n" // r20 r21 r22 r23 + + "ext v8.16b, %18.16b, %18.16b, #8 \n" + "fmla v10.4h, %18.4h, v3.h[0] \n" + "fmla v11.4h, %18.4h, v3.h[4] \n" + "fmla v12.4h, v8.4h, v3.h[1] \n" + "fmla v13.4h, v8.4h, v3.h[5] \n" + "ext v9.16b, %19.16b, %19.16b, #8 \n" + "fmla v10.4h, %19.4h, v3.h[2] \n" + "fmla v11.4h, %19.4h, v3.h[6] \n" + "fmla v12.4h, v9.4h, v3.h[3] \n" + "fmla v13.4h, v9.4h, v3.h[7] \n" + + "ext v4.16b, %20.16b, %20.16b, #8 \n" + "fmla v10.4h, %20.4h, v0.h[0] \n" + "fmla v11.4h, %20.4h, v0.h[4] \n" + "fmla v12.4h, v4.4h, v0.h[1] \n" + "fmla v13.4h, v4.4h, v0.h[5] \n" + "ext v5.16b, %21.16b, %21.16b, #8 \n" + "fmla v10.4h, %21.4h, v0.h[2] \n" + "fmla v11.4h, %21.4h, v0.h[6] \n" + "fmla v12.4h, v5.4h, v0.h[3] \n" + "fmla v13.4h, v5.4h, v0.h[7] \n" + + "ext v6.16b, %22.16b, %22.16b, #8 \n" + "fmla v10.4h, %22.4h, v0.h[4] \n" + "fmla v11.4h, %22.4h, v1.h[0] \n" + "fmla v12.4h, v6.4h, v0.h[5] \n" + "fmla v13.4h, v6.4h, v1.h[1] \n" + "ext v7.16b, %23.16b, %23.16b, #8 \n" + "fmla v10.4h, %23.4h, v0.h[6] \n" + "fmla v11.4h, %23.4h, v1.h[2] \n" + "fmla v12.4h, v7.4h, v0.h[7] \n" + "fmla v13.4h, v7.4h, v1.h[3] \n" + + "ext v8.16b, %24.16b, %24.16b, #8 \n" + "fmla v10.4h, %24.4h, v1.h[0] \n" + "fmla v11.4h, %24.4h, v1.h[4] \n" + "fmla v12.4h, v8.4h, v1.h[1] \n" + "fmla v13.4h, v8.4h, v1.h[5] \n" + "ext v9.16b, %25.16b, %25.16b, #8 \n" + "fmla v10.4h, %25.4h, v1.h[2] \n" + "fmla v11.4h, %25.4h, v1.h[6] \n" + "fmla v12.4h, v9.4h, v1.h[3] \n" + "fmla v13.4h, v9.4h, v1.h[7] \n" + + "add %1, %1, #16 \n" + + "fadd v10.4h, v10.4h, v12.4h \n" + + "add %2, %2, #16 \n" + + "fadd v11.4h, v11.4h, v13.4h \n" + + "add %3, %3, #16 \n" + + "st1 {v10.4h, v11.4h}, [%0], #16 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00_01), // %8 + "w"(_k00_23), // %9 + "w"(_k01_01), // %10 + "w"(_k01_23), // %11 + "w"(_k02_01), // %12 + "w"(_k02_23), // %13 + "w"(_k10_01), // %14 + "w"(_k10_23), // %15 + "w"(_k11_01), // %16 + "w"(_k11_23), // %17 + "w"(_k12_01), // %18 + "w"(_k12_23), // %19 + "w"(_k20_01), // %20 + "w"(_k20_23), // %21 + "w"(_k21_01), // %22 + "w"(_k21_23), // %23 + "w"(_k22_01), // %24 + "w"(_k22_23) // %25 + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13"); + } + for (; j < outw; j++) + { + asm volatile( + "prfm pldl1keep, [%1, #192] \n" + "ld1 {v0.4h, v1.4h, v2.4h}, [%1] \n" // r00 r01 r02 + + "prfm pldl1keep, [%0, #64] \n" + "ld1 {v13.4h}, [%0] \n" // sum0 + + "ext v6.16b, %8.16b, %8.16b, #8 \n" + "fmul v10.4h, %8.4h, v0.h[0] \n" + "fmul v11.4h, v6.4h, v0.h[1] \n" + "ext v7.16b, %9.16b, %9.16b, #8 \n" + "fmul v12.4h, %9.4h, v0.h[2] \n" + "fmla v13.4h, v7.4h, v0.h[3] \n" + + "ext v8.16b, %10.16b, %10.16b, #8 \n" + "fmla v10.4h, %10.4h, v1.h[0] \n" + "fmla v11.4h, v8.4h, v1.h[1] \n" + "ext v9.16b, %11.16b, %11.16b, #8 \n" + "fmla v12.4h, %11.4h, v1.h[2] \n" + "fmla v13.4h, v9.4h, v1.h[3] \n" + + "prfm pldl1keep, [%2, #192] \n" + "ld1 {v3.4h, v4.4h, v5.4h}, [%2] \n" // r10 r11 r12 + + "ext v6.16b, %12.16b, %12.16b, #8 \n" + "fmla v10.4h, %12.4h, v2.h[0] \n" + "fmla v11.4h, v6.4h, v2.h[1] \n" + "ext v7.16b, %13.16b, %13.16b, #8 \n" + "fmla v12.4h, %13.4h, v2.h[2] \n" + "fmla v13.4h, v7.4h, v2.h[3] \n" + + "ext v8.16b, %14.16b, %14.16b, #8 \n" + "fmla v10.4h, %14.4h, v3.h[0] \n" + "fmla v11.4h, v8.4h, v3.h[1] \n" + "ext v9.16b, %15.16b, %15.16b, #8 \n" + "fmla v12.4h, %15.4h, v3.h[2] \n" + "fmla v13.4h, v9.4h, v3.h[3] \n" + + "ext v6.16b, %16.16b, %16.16b, #8 \n" + "fmla v10.4h, %16.4h, v4.h[0] \n" + "fmla v11.4h, v6.4h, v4.h[1] \n" + "ext v7.16b, %17.16b, %17.16b, #8 \n" + "fmla v12.4h, %17.4h, v4.h[2] \n" + "fmla v13.4h, v7.4h, v4.h[3] \n" + + "prfm pldl1keep, [%3, #192] \n" + "ld1 {v0.4h, v1.4h, v2.4h}, [%3] \n" // r20 r21 r22 + + "ext v8.16b, %18.16b, %18.16b, #8 \n" + "fmla v10.4h, %18.4h, v5.h[0] \n" + "fmla v11.4h, v8.4h, v5.h[1] \n" + "ext v9.16b, %19.16b, %19.16b, #8 \n" + "fmla v12.4h, %19.4h, v5.h[2] \n" + "fmla v13.4h, v9.4h, v5.h[3] \n" + + "ext v6.16b, %20.16b, %20.16b, #8 \n" + "fmla v10.4h, %20.4h, v0.h[0] \n" + "fmla v11.4h, v6.4h, v0.h[1] \n" + "ext v7.16b, %21.16b, %21.16b, #8 \n" + "fmla v12.4h, %21.4h, v0.h[2] \n" + "fmla v13.4h, v7.4h, v0.h[3] \n" + + "ext v8.16b, %22.16b, %22.16b, #8 \n" + "fmla v10.4h, %22.4h, v1.h[0] \n" + "fmla v11.4h, v8.4h, v1.h[1] \n" + "ext v9.16b, %23.16b, %23.16b, #8 \n" + "fmla v12.4h, %23.4h, v1.h[2] \n" + "fmla v13.4h, v9.4h, v1.h[3] \n" + + "ext v6.16b, %24.16b, %24.16b, #8 \n" + "fmla v10.4h, %24.4h, v2.h[0] \n" + "fmla v11.4h, v6.4h, v2.h[1] \n" + "ext v7.16b, %25.16b, %25.16b, #8 \n" + "fmla v12.4h, %25.4h, v2.h[2] \n" + "fmla v13.4h, v7.4h, v2.h[3] \n" + + "fadd v10.4h, v10.4h, v11.4h \n" + + "add %1, %1, #8 \n" + + "fadd v12.4h, v12.4h, v13.4h \n" + + "add %2, %2, #8 \n" + + "fadd v10.4h, v10.4h, v12.4h \n" + + "add %3, %3, #8 \n" + + "st1 {v10.4h}, [%0], #8 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2) // %3 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "w"(_k00_01), // %8 + "w"(_k00_23), // %9 + "w"(_k01_01), // %10 + "w"(_k01_23), // %11 + "w"(_k02_01), // %12 + "w"(_k02_23), // %13 + "w"(_k10_01), // %14 + "w"(_k10_23), // %15 + "w"(_k11_01), // %16 + "w"(_k11_23), // %17 + "w"(_k12_01), // %18 + "w"(_k12_23), // %19 + "w"(_k20_01), // %20 + "w"(_k20_23), // %21 + "w"(_k21_01), // %22 + "w"(_k21_23), // %23 + "w"(_k22_01), // %24 + "w"(_k22_23) // %25 + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13"); + } + + r0 += 8; + r1 += 8; + r2 += 8; + } + } + } +} diff --git a/src/layer/arm/convolution_3x3_pack8_fp16s.h b/src/layer/arm/convolution_3x3_pack8_fp16s.h index e1c9a46fc..12e4dbf3b 100644 --- a/src/layer/arm/convolution_3x3_pack8_fp16s.h +++ b/src/layer/arm/convolution_3x3_pack8_fp16s.h @@ -2244,6 +2244,969 @@ static void conv3x3s1_winograd42_pack8_fp16sa_neon(const Mat& bottom_blob, Mat& copy_cut_border(top_blob_bordered, top_blob, 0, top_blob_bordered.h - top_blob.h, 0, top_blob_bordered.w - top_blob.w, opt); } +static void conv3x3s1_pack8_fp16sa_neon(const Mat& bottom_blob, Mat& top_blob, const Mat& kernel, const Mat& _bias, const Option& opt) +{ + int w = bottom_blob.w; + int inch = bottom_blob.c; + int outw = top_blob.w; + int outh = top_blob.h; + int outch = top_blob.c; + + const __fp16* bias = _bias; + + #pragma omp parallel for num_threads(opt.num_threads) + for (int p = 0; p < outch; p++) + { + Mat out0 = top_blob.channel(p); + + float16x8_t _bias0 = bias ? vld1q_f16(bias + p * 8) : vdupq_n_f16(0.f); + out0.fill(_bias0); + + for (int q = 0; q < inch; q++) + { + __fp16* outptr0 = out0.row<__fp16>(0); + + const Mat img0 = bottom_blob.channel(q); + + const __fp16* r0 = img0.row(0); + const __fp16* r1 = img0.row(1); + const __fp16* r2 = img0.row(2); + + const __fp16* kptr = kernel.channel(p).row(q); + + int i = 0; + for (; i < outh; i++) + { + int j = 0; + for (; j + 3 < outw; j += 4) + { + asm volatile( + "prfm pldl1keep, [%1, #512] \n" + "ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [%1], #64 \n" // r00 r01 r02 r03 + + "prfm pldl1keep, [%0, #512] \n" + "ld1 {v28.8h, v29.8h, v30.8h, v31.8h}, [%0] \n" // sum0 + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "prfm pldl1keep, [%1, #256] \n" + "ld1 {v4.8h, v5.8h}, [%1] \n" // r04 r05 + + "fmla v28.8h, v16.8h, v0.h[0] \n" + "fmla v29.8h, v16.8h, v1.h[0] \n" + "fmla v30.8h, v16.8h, v2.h[0] \n" + "fmla v31.8h, v16.8h, v3.h[0] \n" + + "fmla v28.8h, v17.8h, v0.h[1] \n" + "fmla v29.8h, v17.8h, v1.h[1] \n" + "fmla v30.8h, v17.8h, v2.h[1] \n" + "fmla v31.8h, v17.8h, v3.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v0.h[2] \n" + "fmla v29.8h, v18.8h, v1.h[2] \n" + "fmla v30.8h, v18.8h, v2.h[2] \n" + "fmla v31.8h, v18.8h, v3.h[2] \n" + + "fmla v28.8h, v19.8h, v0.h[3] \n" + "fmla v29.8h, v19.8h, v1.h[3] \n" + "fmla v30.8h, v19.8h, v2.h[3] \n" + "fmla v31.8h, v19.8h, v3.h[3] \n" + + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v20.8h, v1.h[4] \n" + "fmla v30.8h, v20.8h, v2.h[4] \n" + "fmla v31.8h, v20.8h, v3.h[4] \n" + + "fmla v28.8h, v21.8h, v0.h[5] \n" + "fmla v29.8h, v21.8h, v1.h[5] \n" + "fmla v30.8h, v21.8h, v2.h[5] \n" + "fmla v31.8h, v21.8h, v3.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v0.h[6] \n" + "fmla v29.8h, v22.8h, v1.h[6] \n" + "fmla v30.8h, v22.8h, v2.h[6] \n" + "fmla v31.8h, v22.8h, v3.h[6] \n" + + "fmla v28.8h, v23.8h, v0.h[7] \n" + "fmla v29.8h, v23.8h, v1.h[7] \n" + "fmla v30.8h, v23.8h, v2.h[7] \n" + "fmla v31.8h, v23.8h, v3.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v16.8h, v2.h[0] \n" + "fmla v30.8h, v16.8h, v3.h[0] \n" + "fmla v31.8h, v16.8h, v4.h[0] \n" + + "fmla v28.8h, v17.8h, v1.h[1] \n" + "fmla v29.8h, v17.8h, v2.h[1] \n" + "fmla v30.8h, v17.8h, v3.h[1] \n" + "fmla v31.8h, v17.8h, v4.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v1.h[2] \n" + "fmla v29.8h, v18.8h, v2.h[2] \n" + "fmla v30.8h, v18.8h, v3.h[2] \n" + "fmla v31.8h, v18.8h, v4.h[2] \n" + + "fmla v28.8h, v19.8h, v1.h[3] \n" + "fmla v29.8h, v19.8h, v2.h[3] \n" + "fmla v30.8h, v19.8h, v3.h[3] \n" + "fmla v31.8h, v19.8h, v4.h[3] \n" + + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v20.8h, v2.h[4] \n" + "fmla v30.8h, v20.8h, v3.h[4] \n" + "fmla v31.8h, v20.8h, v4.h[4] \n" + + "fmla v28.8h, v21.8h, v1.h[5] \n" + "fmla v29.8h, v21.8h, v2.h[5] \n" + "fmla v30.8h, v21.8h, v3.h[5] \n" + "fmla v31.8h, v21.8h, v4.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v1.h[6] \n" + "fmla v29.8h, v22.8h, v2.h[6] \n" + "fmla v30.8h, v22.8h, v3.h[6] \n" + "fmla v31.8h, v22.8h, v4.h[6] \n" + + "fmla v28.8h, v23.8h, v1.h[7] \n" + "fmla v29.8h, v23.8h, v2.h[7] \n" + "fmla v30.8h, v23.8h, v3.h[7] \n" + "fmla v31.8h, v23.8h, v4.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v16.8h, v3.h[0] \n" + "fmla v30.8h, v16.8h, v4.h[0] \n" + "fmla v31.8h, v16.8h, v5.h[0] \n" + + "fmla v28.8h, v17.8h, v2.h[1] \n" + "fmla v29.8h, v17.8h, v3.h[1] \n" + "fmla v30.8h, v17.8h, v4.h[1] \n" + "fmla v31.8h, v17.8h, v5.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v2.h[2] \n" + "fmla v29.8h, v18.8h, v3.h[2] \n" + "fmla v30.8h, v18.8h, v4.h[2] \n" + "fmla v31.8h, v18.8h, v5.h[2] \n" + + "fmla v28.8h, v19.8h, v2.h[3] \n" + "fmla v29.8h, v19.8h, v3.h[3] \n" + "fmla v30.8h, v19.8h, v4.h[3] \n" + "fmla v31.8h, v19.8h, v5.h[3] \n" + + "prfm pldl1keep, [%2, #512] \n" + "ld1 {v8.8h, v9.8h, v10.8h, v11.8h}, [%2], #64 \n" // r10 r11 r12 r13 + + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v20.8h, v3.h[4] \n" + "fmla v30.8h, v20.8h, v4.h[4] \n" + "fmla v31.8h, v20.8h, v5.h[4] \n" + + "fmla v28.8h, v21.8h, v2.h[5] \n" + "fmla v29.8h, v21.8h, v3.h[5] \n" + "fmla v30.8h, v21.8h, v4.h[5] \n" + "fmla v31.8h, v21.8h, v5.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v2.h[6] \n" + "fmla v29.8h, v22.8h, v3.h[6] \n" + "fmla v30.8h, v22.8h, v4.h[6] \n" + "fmla v31.8h, v22.8h, v5.h[6] \n" + + "fmla v28.8h, v23.8h, v2.h[7] \n" + "fmla v29.8h, v23.8h, v3.h[7] \n" + "fmla v30.8h, v23.8h, v4.h[7] \n" + "fmla v31.8h, v23.8h, v5.h[7] \n" + + "prfm pldl1keep, [%2, #256] \n" + "ld1 {v12.8h, v13.8h}, [%2] \n" // r14 r15 + + "fmla v28.8h, v16.8h, v8.h[0] \n" + "fmla v29.8h, v16.8h, v9.h[0] \n" + "fmla v30.8h, v16.8h, v10.h[0] \n" + "fmla v31.8h, v16.8h, v11.h[0] \n" + + "fmla v28.8h, v17.8h, v8.h[1] \n" + "fmla v29.8h, v17.8h, v9.h[1] \n" + "fmla v30.8h, v17.8h, v10.h[1] \n" + "fmla v31.8h, v17.8h, v11.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v8.h[2] \n" + "fmla v29.8h, v18.8h, v9.h[2] \n" + "fmla v30.8h, v18.8h, v10.h[2] \n" + "fmla v31.8h, v18.8h, v11.h[2] \n" + + "fmla v28.8h, v19.8h, v8.h[3] \n" + "fmla v29.8h, v19.8h, v9.h[3] \n" + "fmla v30.8h, v19.8h, v10.h[3] \n" + "fmla v31.8h, v19.8h, v11.h[3] \n" + + "fmla v28.8h, v20.8h, v8.h[4] \n" + "fmla v29.8h, v20.8h, v9.h[4] \n" + "fmla v30.8h, v20.8h, v10.h[4] \n" + "fmla v31.8h, v20.8h, v11.h[4] \n" + + "fmla v28.8h, v21.8h, v8.h[5] \n" + "fmla v29.8h, v21.8h, v9.h[5] \n" + "fmla v30.8h, v21.8h, v10.h[5] \n" + "fmla v31.8h, v21.8h, v11.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v8.h[6] \n" + "fmla v29.8h, v22.8h, v9.h[6] \n" + "fmla v30.8h, v22.8h, v10.h[6] \n" + "fmla v31.8h, v22.8h, v11.h[6] \n" + + "fmla v28.8h, v23.8h, v8.h[7] \n" + "fmla v29.8h, v23.8h, v9.h[7] \n" + "fmla v30.8h, v23.8h, v10.h[7] \n" + "fmla v31.8h, v23.8h, v11.h[7] \n" + + "fmla v28.8h, v16.8h, v9.h[0] \n" + "fmla v29.8h, v16.8h, v10.h[0] \n" + "fmla v30.8h, v16.8h, v11.h[0] \n" + "fmla v31.8h, v16.8h, v12.h[0] \n" + + "fmla v28.8h, v17.8h, v9.h[1] \n" + "fmla v29.8h, v17.8h, v10.h[1] \n" + "fmla v30.8h, v17.8h, v11.h[1] \n" + "fmla v31.8h, v17.8h, v12.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v9.h[2] \n" + "fmla v29.8h, v18.8h, v10.h[2] \n" + "fmla v30.8h, v18.8h, v11.h[2] \n" + "fmla v31.8h, v18.8h, v12.h[2] \n" + + "fmla v28.8h, v19.8h, v9.h[3] \n" + "fmla v29.8h, v19.8h, v10.h[3] \n" + "fmla v30.8h, v19.8h, v11.h[3] \n" + "fmla v31.8h, v19.8h, v12.h[3] \n" + + "fmla v28.8h, v20.8h, v9.h[4] \n" + "fmla v29.8h, v20.8h, v10.h[4] \n" + "fmla v30.8h, v20.8h, v11.h[4] \n" + "fmla v31.8h, v20.8h, v12.h[4] \n" + + "fmla v28.8h, v21.8h, v9.h[5] \n" + "fmla v29.8h, v21.8h, v10.h[5] \n" + "fmla v30.8h, v21.8h, v11.h[5] \n" + "fmla v31.8h, v21.8h, v12.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v9.h[6] \n" + "fmla v29.8h, v22.8h, v10.h[6] \n" + "fmla v30.8h, v22.8h, v11.h[6] \n" + "fmla v31.8h, v22.8h, v12.h[6] \n" + + "fmla v28.8h, v23.8h, v9.h[7] \n" + "fmla v29.8h, v23.8h, v10.h[7] \n" + "fmla v30.8h, v23.8h, v11.h[7] \n" + "fmla v31.8h, v23.8h, v12.h[7] \n" + + "fmla v28.8h, v16.8h, v10.h[0] \n" + "fmla v29.8h, v16.8h, v11.h[0] \n" + "fmla v30.8h, v16.8h, v12.h[0] \n" + "fmla v31.8h, v16.8h, v13.h[0] \n" + + "fmla v28.8h, v17.8h, v10.h[1] \n" + "fmla v29.8h, v17.8h, v11.h[1] \n" + "fmla v30.8h, v17.8h, v12.h[1] \n" + "fmla v31.8h, v17.8h, v13.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v10.h[2] \n" + "fmla v29.8h, v18.8h, v11.h[2] \n" + "fmla v30.8h, v18.8h, v12.h[2] \n" + "fmla v31.8h, v18.8h, v13.h[2] \n" + + "fmla v28.8h, v19.8h, v10.h[3] \n" + "fmla v29.8h, v19.8h, v11.h[3] \n" + "fmla v30.8h, v19.8h, v12.h[3] \n" + "fmla v31.8h, v19.8h, v13.h[3] \n" + + "prfm pldl1keep, [%3, #512] \n" + "ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [%3], #64 \n" // r20 r21 r22 r23 + + "fmla v28.8h, v20.8h, v10.h[4] \n" + "fmla v29.8h, v20.8h, v11.h[4] \n" + "fmla v30.8h, v20.8h, v12.h[4] \n" + "fmla v31.8h, v20.8h, v13.h[4] \n" + + "fmla v28.8h, v21.8h, v10.h[5] \n" + "fmla v29.8h, v21.8h, v11.h[5] \n" + "fmla v30.8h, v21.8h, v12.h[5] \n" + "fmla v31.8h, v21.8h, v13.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v10.h[6] \n" + "fmla v29.8h, v22.8h, v11.h[6] \n" + "fmla v30.8h, v22.8h, v12.h[6] \n" + "fmla v31.8h, v22.8h, v13.h[6] \n" + + "fmla v28.8h, v23.8h, v10.h[7] \n" + "fmla v29.8h, v23.8h, v11.h[7] \n" + "fmla v30.8h, v23.8h, v12.h[7] \n" + "fmla v31.8h, v23.8h, v13.h[7] \n" + + "prfm pldl1keep, [%3, #256] \n" + "ld1 {v4.8h, v5.8h}, [%3] \n" // r24 r25 + + "fmla v28.8h, v16.8h, v0.h[0] \n" + "fmla v29.8h, v16.8h, v1.h[0] \n" + "fmla v30.8h, v16.8h, v2.h[0] \n" + "fmla v31.8h, v16.8h, v3.h[0] \n" + + "fmla v28.8h, v17.8h, v0.h[1] \n" + "fmla v29.8h, v17.8h, v1.h[1] \n" + "fmla v30.8h, v17.8h, v2.h[1] \n" + "fmla v31.8h, v17.8h, v3.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v0.h[2] \n" + "fmla v29.8h, v18.8h, v1.h[2] \n" + "fmla v30.8h, v18.8h, v2.h[2] \n" + "fmla v31.8h, v18.8h, v3.h[2] \n" + + "fmla v28.8h, v19.8h, v0.h[3] \n" + "fmla v29.8h, v19.8h, v1.h[3] \n" + "fmla v30.8h, v19.8h, v2.h[3] \n" + "fmla v31.8h, v19.8h, v3.h[3] \n" + + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v20.8h, v1.h[4] \n" + "fmla v30.8h, v20.8h, v2.h[4] \n" + "fmla v31.8h, v20.8h, v3.h[4] \n" + + "fmla v28.8h, v21.8h, v0.h[5] \n" + "fmla v29.8h, v21.8h, v1.h[5] \n" + "fmla v30.8h, v21.8h, v2.h[5] \n" + "fmla v31.8h, v21.8h, v3.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v0.h[6] \n" + "fmla v29.8h, v22.8h, v1.h[6] \n" + "fmla v30.8h, v22.8h, v2.h[6] \n" + "fmla v31.8h, v22.8h, v3.h[6] \n" + + "fmla v28.8h, v23.8h, v0.h[7] \n" + "fmla v29.8h, v23.8h, v1.h[7] \n" + "fmla v30.8h, v23.8h, v2.h[7] \n" + "fmla v31.8h, v23.8h, v3.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v16.8h, v2.h[0] \n" + "fmla v30.8h, v16.8h, v3.h[0] \n" + "fmla v31.8h, v16.8h, v4.h[0] \n" + + "fmla v28.8h, v17.8h, v1.h[1] \n" + "fmla v29.8h, v17.8h, v2.h[1] \n" + "fmla v30.8h, v17.8h, v3.h[1] \n" + "fmla v31.8h, v17.8h, v4.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v1.h[2] \n" + "fmla v29.8h, v18.8h, v2.h[2] \n" + "fmla v30.8h, v18.8h, v3.h[2] \n" + "fmla v31.8h, v18.8h, v4.h[2] \n" + + "fmla v28.8h, v19.8h, v1.h[3] \n" + "fmla v29.8h, v19.8h, v2.h[3] \n" + "fmla v30.8h, v19.8h, v3.h[3] \n" + "fmla v31.8h, v19.8h, v4.h[3] \n" + + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v20.8h, v2.h[4] \n" + "fmla v30.8h, v20.8h, v3.h[4] \n" + "fmla v31.8h, v20.8h, v4.h[4] \n" + + "fmla v28.8h, v21.8h, v1.h[5] \n" + "fmla v29.8h, v21.8h, v2.h[5] \n" + "fmla v30.8h, v21.8h, v3.h[5] \n" + "fmla v31.8h, v21.8h, v4.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v1.h[6] \n" + "fmla v29.8h, v22.8h, v2.h[6] \n" + "fmla v30.8h, v22.8h, v3.h[6] \n" + "fmla v31.8h, v22.8h, v4.h[6] \n" + + "fmla v28.8h, v23.8h, v1.h[7] \n" + "fmla v29.8h, v23.8h, v2.h[7] \n" + "fmla v30.8h, v23.8h, v3.h[7] \n" + "fmla v31.8h, v23.8h, v4.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v16.8h, v3.h[0] \n" + "fmla v30.8h, v16.8h, v4.h[0] \n" + "fmla v31.8h, v16.8h, v5.h[0] \n" + + "fmla v28.8h, v17.8h, v2.h[1] \n" + "fmla v29.8h, v17.8h, v3.h[1] \n" + "fmla v30.8h, v17.8h, v4.h[1] \n" + "fmla v31.8h, v17.8h, v5.h[1] \n" + + // "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4] \n" + + "fmla v28.8h, v18.8h, v2.h[2] \n" + "fmla v29.8h, v18.8h, v3.h[2] \n" + "fmla v30.8h, v18.8h, v4.h[2] \n" + "fmla v31.8h, v18.8h, v5.h[2] \n" + + "fmla v28.8h, v19.8h, v2.h[3] \n" + "fmla v29.8h, v19.8h, v3.h[3] \n" + "fmla v30.8h, v19.8h, v4.h[3] \n" + "fmla v31.8h, v19.8h, v5.h[3] \n" + + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v20.8h, v3.h[4] \n" + "fmla v30.8h, v20.8h, v4.h[4] \n" + "fmla v31.8h, v20.8h, v5.h[4] \n" + + "fmla v28.8h, v21.8h, v2.h[5] \n" + "fmla v29.8h, v21.8h, v3.h[5] \n" + "fmla v30.8h, v21.8h, v4.h[5] \n" + "fmla v31.8h, v21.8h, v5.h[5] \n" + + "fmla v28.8h, v22.8h, v2.h[6] \n" + "fmla v29.8h, v22.8h, v3.h[6] \n" + "fmla v30.8h, v22.8h, v4.h[6] \n" + "fmla v31.8h, v22.8h, v5.h[6] \n" + + "fmla v28.8h, v23.8h, v2.h[7] \n" + "fmla v29.8h, v23.8h, v3.h[7] \n" + "fmla v30.8h, v23.8h, v4.h[7] \n" + "fmla v31.8h, v23.8h, v5.h[7] \n" + + "sub %4, %4, #1088 \n" // kptr -= 8.5 * 64; + + "st1 {v28.8h, v29.8h, v30.8h, v31.8h}, [%0], #64 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2), // %3 + "=r"(kptr) // %4 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "4"(kptr) + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v28", "v29", "v30", "v31"); + } + for (; j + 1 < outw; j += 2) + { + asm volatile( + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "prfm pldl1keep, [%1, #512] \n" + "ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [%1] \n" // r00 r01 r02 r03 + + "prfm pldl1keep, [%0, #256] \n" + "ld1 {v30.8h, v31.8h}, [%0] \n" // sum0 + + "fmul v28.8h, v16.8h, v0.h[0] \n" + "fmul v29.8h, v16.8h, v1.h[0] \n" + "fmla v30.8h, v17.8h, v0.h[1] \n" + "fmla v31.8h, v17.8h, v1.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v0.h[2] \n" + "fmla v29.8h, v18.8h, v1.h[2] \n" + "fmla v30.8h, v19.8h, v0.h[3] \n" + "fmla v31.8h, v19.8h, v1.h[3] \n" + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v20.8h, v1.h[4] \n" + "fmla v30.8h, v21.8h, v0.h[5] \n" + "fmla v31.8h, v21.8h, v1.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v0.h[6] \n" + "fmla v29.8h, v22.8h, v1.h[6] \n" + "fmla v30.8h, v23.8h, v0.h[7] \n" + "fmla v31.8h, v23.8h, v1.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v16.8h, v2.h[0] \n" + "fmla v30.8h, v17.8h, v1.h[1] \n" + "fmla v31.8h, v17.8h, v2.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v1.h[2] \n" + "fmla v29.8h, v18.8h, v2.h[2] \n" + "fmla v30.8h, v19.8h, v1.h[3] \n" + "fmla v31.8h, v19.8h, v2.h[3] \n" + + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v20.8h, v2.h[4] \n" + "fmla v30.8h, v21.8h, v1.h[5] \n" + "fmla v31.8h, v21.8h, v2.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v1.h[6] \n" + "fmla v29.8h, v22.8h, v2.h[6] \n" + "fmla v30.8h, v23.8h, v1.h[7] \n" + "fmla v31.8h, v23.8h, v2.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v16.8h, v3.h[0] \n" + "fmla v30.8h, v17.8h, v2.h[1] \n" + "fmla v31.8h, v17.8h, v3.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v2.h[2] \n" + "fmla v29.8h, v18.8h, v3.h[2] \n" + "fmla v30.8h, v19.8h, v2.h[3] \n" + "fmla v31.8h, v19.8h, v3.h[3] \n" + + "prfm pldl1keep, [%2, #512] \n" + "ld1 {v4.8h, v5.8h, v6.8h, v7.8h}, [%2] \n" // r10 r11 r12 r13 + + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v20.8h, v3.h[4] \n" + "fmla v30.8h, v21.8h, v2.h[5] \n" + "fmla v31.8h, v21.8h, v3.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v2.h[6] \n" + "fmla v29.8h, v22.8h, v3.h[6] \n" + "fmla v30.8h, v23.8h, v2.h[7] \n" + "fmla v31.8h, v23.8h, v3.h[7] \n" + + "fmla v28.8h, v16.8h, v4.h[0] \n" + "fmla v29.8h, v16.8h, v5.h[0] \n" + "fmla v30.8h, v17.8h, v4.h[1] \n" + "fmla v31.8h, v17.8h, v5.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v4.h[2] \n" + "fmla v29.8h, v18.8h, v5.h[2] \n" + "fmla v30.8h, v19.8h, v4.h[3] \n" + "fmla v31.8h, v19.8h, v5.h[3] \n" + "fmla v28.8h, v20.8h, v4.h[4] \n" + "fmla v29.8h, v20.8h, v5.h[4] \n" + "fmla v30.8h, v21.8h, v4.h[5] \n" + "fmla v31.8h, v21.8h, v5.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v4.h[6] \n" + "fmla v29.8h, v22.8h, v5.h[6] \n" + "fmla v30.8h, v23.8h, v4.h[7] \n" + "fmla v31.8h, v23.8h, v5.h[7] \n" + + "fmla v28.8h, v16.8h, v5.h[0] \n" + "fmla v29.8h, v16.8h, v6.h[0] \n" + "fmla v30.8h, v17.8h, v5.h[1] \n" + "fmla v31.8h, v17.8h, v6.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v5.h[2] \n" + "fmla v29.8h, v18.8h, v6.h[2] \n" + "fmla v30.8h, v19.8h, v5.h[3] \n" + "fmla v31.8h, v19.8h, v6.h[3] \n" + + "fmla v28.8h, v20.8h, v5.h[4] \n" + "fmla v29.8h, v20.8h, v6.h[4] \n" + "fmla v30.8h, v21.8h, v5.h[5] \n" + "fmla v31.8h, v21.8h, v6.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v5.h[6] \n" + "fmla v29.8h, v22.8h, v6.h[6] \n" + "fmla v30.8h, v23.8h, v5.h[7] \n" + "fmla v31.8h, v23.8h, v6.h[7] \n" + + "fmla v28.8h, v16.8h, v6.h[0] \n" + "fmla v29.8h, v16.8h, v7.h[0] \n" + "fmla v30.8h, v17.8h, v6.h[1] \n" + "fmla v31.8h, v17.8h, v7.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v6.h[2] \n" + "fmla v29.8h, v18.8h, v7.h[2] \n" + "fmla v30.8h, v19.8h, v6.h[3] \n" + "fmla v31.8h, v19.8h, v7.h[3] \n" + + "prfm pldl1keep, [%3, #512] \n" + "ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [%3] \n" // r20 r21 r22 r23 + + "fmla v28.8h, v20.8h, v6.h[4] \n" + "fmla v29.8h, v20.8h, v7.h[4] \n" + "fmla v30.8h, v21.8h, v6.h[5] \n" + "fmla v31.8h, v21.8h, v7.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v6.h[6] \n" + "fmla v29.8h, v22.8h, v7.h[6] \n" + "fmla v30.8h, v23.8h, v6.h[7] \n" + "fmla v31.8h, v23.8h, v7.h[7] \n" + + "fmla v28.8h, v16.8h, v0.h[0] \n" + "fmla v29.8h, v16.8h, v1.h[0] \n" + "fmla v30.8h, v17.8h, v0.h[1] \n" + "fmla v31.8h, v17.8h, v1.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v0.h[2] \n" + "fmla v29.8h, v18.8h, v1.h[2] \n" + "fmla v30.8h, v19.8h, v0.h[3] \n" + "fmla v31.8h, v19.8h, v1.h[3] \n" + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v20.8h, v1.h[4] \n" + "fmla v30.8h, v21.8h, v0.h[5] \n" + "fmla v31.8h, v21.8h, v1.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v0.h[6] \n" + "fmla v29.8h, v22.8h, v1.h[6] \n" + "fmla v30.8h, v23.8h, v0.h[7] \n" + "fmla v31.8h, v23.8h, v1.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v16.8h, v2.h[0] \n" + "fmla v30.8h, v17.8h, v1.h[1] \n" + "fmla v31.8h, v17.8h, v2.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v28.8h, v18.8h, v1.h[2] \n" + "fmla v29.8h, v18.8h, v2.h[2] \n" + "fmla v30.8h, v19.8h, v1.h[3] \n" + "fmla v31.8h, v19.8h, v2.h[3] \n" + + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v20.8h, v2.h[4] \n" + "fmla v30.8h, v21.8h, v1.h[5] \n" + "fmla v31.8h, v21.8h, v2.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v28.8h, v22.8h, v1.h[6] \n" + "fmla v29.8h, v22.8h, v2.h[6] \n" + "fmla v30.8h, v23.8h, v1.h[7] \n" + "fmla v31.8h, v23.8h, v2.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v16.8h, v3.h[0] \n" + "fmla v30.8h, v17.8h, v2.h[1] \n" + "fmla v31.8h, v17.8h, v3.h[1] \n" + + // "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4] \n" + + "fmla v28.8h, v18.8h, v2.h[2] \n" + "fmla v29.8h, v18.8h, v3.h[2] \n" + "fmla v30.8h, v19.8h, v2.h[3] \n" + "fmla v31.8h, v19.8h, v3.h[3] \n" + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v20.8h, v3.h[4] \n" + "fmla v30.8h, v21.8h, v2.h[5] \n" + "fmla v31.8h, v21.8h, v3.h[5] \n" + "fmla v28.8h, v22.8h, v2.h[6] \n" + "fmla v29.8h, v22.8h, v3.h[6] \n" + "fmla v30.8h, v23.8h, v2.h[7] \n" + "fmla v31.8h, v23.8h, v3.h[7] \n" + + "add %1, %1, #32 \n" + + "add %2, %2, #32 \n" + + "add %3, %3, #32 \n" + + "fadd v28.8h, v28.8h, v30.8h \n" + "fadd v29.8h, v29.8h, v31.8h \n" + + "sub %4, %4, #1088 \n" // kptr -= 8.5 * 64; + + "st1 {v28.8h, v29.8h}, [%0], #32 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2), // %3 + "=r"(kptr) // %4 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "4"(kptr) + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v28", "v29", "v30", "v31"); + } + for (; j < outw; j++) + { + asm volatile( + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "prfm pldl1keep, [%1, #384] \n" + "ld1 {v0.8h, v1.8h, v2.8h}, [%1] \n" // r00 r01 r02 + + "prfm pldl1keep, [%0, #128] \n" + "ld1 {v31.8h}, [%0] \n" // sum0 + + "fmul v28.8h, v16.8h, v0.h[0] \n" + "fmul v29.8h, v17.8h, v0.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmul v30.8h, v18.8h, v0.h[2] \n" + "fmla v31.8h, v19.8h, v0.h[3] \n" + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v21.8h, v0.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v0.h[6] \n" + "fmla v31.8h, v23.8h, v0.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v17.8h, v1.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v1.h[2] \n" + "fmla v31.8h, v19.8h, v1.h[3] \n" + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v21.8h, v1.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v1.h[6] \n" + "fmla v31.8h, v23.8h, v1.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v17.8h, v2.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v2.h[2] \n" + "fmla v31.8h, v19.8h, v2.h[3] \n" + + "prfm pldl1keep, [%2, #384] \n" + "ld1 {v3.8h, v4.8h, v5.8h}, [%2] \n" // r10 r11 r12 + + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v21.8h, v2.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v2.h[6] \n" + "fmla v31.8h, v23.8h, v2.h[7] \n" + + "fmla v28.8h, v16.8h, v3.h[0] \n" + "fmla v29.8h, v17.8h, v3.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v3.h[2] \n" + "fmla v31.8h, v19.8h, v3.h[3] \n" + "fmla v28.8h, v20.8h, v3.h[4] \n" + "fmla v29.8h, v21.8h, v3.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v3.h[6] \n" + "fmla v31.8h, v23.8h, v3.h[7] \n" + + "fmla v28.8h, v16.8h, v4.h[0] \n" + "fmla v29.8h, v17.8h, v4.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v4.h[2] \n" + "fmla v31.8h, v19.8h, v4.h[3] \n" + "fmla v28.8h, v20.8h, v4.h[4] \n" + "fmla v29.8h, v21.8h, v4.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v4.h[6] \n" + "fmla v31.8h, v23.8h, v4.h[7] \n" + + "fmla v28.8h, v16.8h, v5.h[0] \n" + "fmla v29.8h, v17.8h, v5.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v5.h[2] \n" + "fmla v31.8h, v19.8h, v5.h[3] \n" + + "prfm pldl1keep, [%3, #384] \n" + "ld1 {v0.8h, v1.8h, v2.8h}, [%3] \n" // r20 r21 r22 + + "fmla v28.8h, v20.8h, v5.h[4] \n" + "fmla v29.8h, v21.8h, v5.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v5.h[6] \n" + "fmla v31.8h, v23.8h, v5.h[7] \n" + + "fmla v28.8h, v16.8h, v0.h[0] \n" + "fmla v29.8h, v17.8h, v0.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v0.h[2] \n" + "fmla v31.8h, v19.8h, v0.h[3] \n" + "fmla v28.8h, v20.8h, v0.h[4] \n" + "fmla v29.8h, v21.8h, v0.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v0.h[6] \n" + "fmla v31.8h, v23.8h, v0.h[7] \n" + + "fmla v28.8h, v16.8h, v1.h[0] \n" + "fmla v29.8h, v17.8h, v1.h[1] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4], #64 \n" + + "fmla v30.8h, v18.8h, v1.h[2] \n" + "fmla v31.8h, v19.8h, v1.h[3] \n" + "fmla v28.8h, v20.8h, v1.h[4] \n" + "fmla v29.8h, v21.8h, v1.h[5] \n" + + "prfm pldl1keep, [%4, #512] \n" + "ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [%4], #64 \n" + + "fmla v30.8h, v22.8h, v1.h[6] \n" + "fmla v31.8h, v23.8h, v1.h[7] \n" + + "fmla v28.8h, v16.8h, v2.h[0] \n" + "fmla v29.8h, v17.8h, v2.h[1] \n" + + // "prfm pldl1keep, [%4, #512] \n" + "ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [%4] \n" + + "fmla v30.8h, v18.8h, v2.h[2] \n" + "fmla v31.8h, v19.8h, v2.h[3] \n" + "fmla v28.8h, v20.8h, v2.h[4] \n" + "fmla v29.8h, v21.8h, v2.h[5] \n" + + "add %1, %1, #16 \n" + + "fmla v30.8h, v22.8h, v2.h[6] \n" + "fmla v31.8h, v23.8h, v2.h[7] \n" + + "add %2, %2, #16 \n" + + "fadd v28.8h, v28.8h, v29.8h \n" + "fadd v30.8h, v30.8h, v31.8h \n" + + "add %3, %3, #16 \n" + + "fadd v28.8h, v28.8h, v30.8h \n" + + "sub %4, %4, #1088 \n" // kptr -= 8.5 * 64; + + "st1 {v28.8h}, [%0], #16 \n" + + : "=r"(outptr0), // %0 + "=r"(r0), // %1 + "=r"(r1), // %2 + "=r"(r2), // %3 + "=r"(kptr) // %4 + : "0"(outptr0), + "1"(r0), + "2"(r1), + "3"(r2), + "4"(kptr) + : "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v28", "v29", "v30", "v31"); + } + + r0 += 16; + r1 += 16; + r2 += 16; + } + } + } +} + static void conv3x3s2_pack8_fp16sa_neon(const Mat& bottom_blob, Mat& top_blob, const Mat& kernel, const Mat& _bias, const Option& opt) { int w = bottom_blob.w; diff --git a/src/layer/arm/convolution_arm.cpp b/src/layer/arm/convolution_arm.cpp index e8435f10b..d92c639ba 100644 --- a/src/layer/arm/convolution_arm.cpp +++ b/src/layer/arm/convolution_arm.cpp @@ -104,6 +104,7 @@ namespace ncnn { #include "convolution_1x1_pack8to4_fp16s.h" #include "convolution_3x3_pack4_fp16s.h" #include "convolution_3x3_pack1to8_fp16s.h" +#include "convolution_3x3_pack1to4_fp16s.h" #include "convolution_3x3_pack8_fp16s.h" #include "convolution_3x3_pack8to1_fp16s.h" #include "convolution_3x3_pack8to4_fp16s.h" @@ -955,7 +956,7 @@ int Convolution_arm::create_pipeline_fp16s(const Option& opt) { convolution_im2col_sgemm_transform_kernel_pack8_fp16sa_neon(weight_data, weight_data_fp16, num_input, num_output, kernel_w, kernel_h); } - else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1 && num_input >= 16 && num_output >= 16) { conv3x3s1_winograd64_transform_kernel_pack8_fp16sa_neon(weight_data, weight_data_fp16, num_input, num_output); conv3x3s1_winograd42_transform_kernel_pack8_fp16sa_neon(weight_data, weight_3x3_winograd42_data_pack4, num_input, num_output); @@ -1048,7 +1049,7 @@ int Convolution_arm::create_pipeline_fp16s(const Option& opt) { conv1x1s1_sgemm_transform_kernel_pack4_fp16sa_neon(weight_data, weight_data_fp16, num_input, num_output); } - else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1 && num_input >= 12 && num_output >= 12) { conv3x3s1_winograd64_transform_kernel_pack4_fp16sa_neon(weight_data, weight_data_fp16, num_input, num_output); } @@ -1194,7 +1195,7 @@ int Convolution_arm::forward_fp16sa(const Mat& bottom_blob, Mat& top_blob, const activation->forward_inplace(top_blob, opt); } } - else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1 && num_input >= 16 && num_output >= 16) { // we need more proper conditions if ((w <= 10 || (w >= 15 && w <= 18) || w == 21 || w == 22) && (h <= 10 || (h >= 15 && h <= 18) || h == 21 || h == 22)) @@ -1211,6 +1212,15 @@ int Convolution_arm::forward_fp16sa(const Mat& bottom_blob, Mat& top_blob, const activation->forward_inplace(top_blob, opt); } } + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + { + conv3x3s1_pack8_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, opt); + + if (activation) + { + activation->forward_inplace(top_blob, opt); + } + } else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 2 && stride_h == 2) { // we need more proper conditions @@ -1450,7 +1460,7 @@ int Convolution_arm::forward_fp16sa(const Mat& bottom_blob, Mat& top_blob, const activation->forward_inplace(top_blob, opt); } } - else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1 && num_input >= 12 && num_output >= 12) { // TODO more proper condition conv3x3s1_winograd64_pack4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, opt); @@ -1462,6 +1472,15 @@ int Convolution_arm::forward_fp16sa(const Mat& bottom_blob, Mat& top_blob, const activation->forward_inplace(top_blob, opt); } } + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + { + conv3x3s1_pack4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, opt); + + if (activation) + { + activation->forward_inplace(top_blob, opt); + } + } else { convolution_pack4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, kernel_w, kernel_h, dilation_w, dilation_h, stride_w, stride_h, activation_type, activation_params, opt); @@ -1470,7 +1489,28 @@ int Convolution_arm::forward_fp16sa(const Mat& bottom_blob, Mat& top_blob, const if (elempack == 1 && out_elempack == 4) { - convolution_pack1to4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, kernel_w, kernel_h, dilation_w, dilation_h, stride_w, stride_h, activation_type, activation_params, opt); + if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 1 && stride_h == 1) + { + conv3x3s1_pack1to4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, opt); + + if (activation) + { + activation->forward_inplace(top_blob, opt); + } + } + else if (kernel_w == 3 && kernel_h == 3 && dilation_w == 1 && dilation_h == 1 && stride_w == 2 && stride_h == 2) + { + conv3x3s2_pack1to4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, opt); + + if (activation) + { + activation->forward_inplace(top_blob, opt); + } + } + else + { + convolution_pack1to4_fp16sa_neon(bottom_blob_bordered, top_blob, weight_data_fp16, bias_data_fp16, kernel_w, kernel_h, dilation_w, dilation_h, stride_w, stride_h, activation_type, activation_params, opt); + } } if (elempack == 4 && out_elempack == 1) diff --git a/tests/test_convolution.cpp b/tests/test_convolution.cpp index 766a086f7..66a0dd21f 100644 --- a/tests/test_convolution.cpp +++ b/tests/test_convolution.cpp @@ -114,6 +114,10 @@ static int test_convolution_0() } return 0 + || test_convolution(7, 5, 1, 4, 3, 1, 1, 1, 1) + || test_convolution(14, 5, 1, 4, 3, 1, 2, 1, 1) + || test_convolution(15, 11, 4, 4, 3, 1, 1, 1, 1) + || test_convolution(15, 11, 8, 8, 3, 1, 1, 1, 1) || test_convolution(11, 11, 8, 16, 3, 1, 1, 1, 1) || test_convolution(13, 16, 16, 24, 3, 1, 1, 1, 1) || test_convolution(8, 8, 16, 24, 3, 1, 1, 1, 0)