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the zfh detector hacking

tags/20210720
nihuini 5 years ago
parent
commit
76b478f59b
2 changed files with 5 additions and 114 deletions
  1. +0
    -99
      .github/workflows/elf-riscv64-cpu-gcc.yml
  2. +5
    -15
      src/cpu.cpp

+ 0
- 99
.github/workflows/elf-riscv64-cpu-gcc.yml View File

@@ -7,105 +7,6 @@ on:
branches: [master]
paths-ignore: ['**.md']
jobs:
newlib-rv64gcv-gcc:
runs-on: ubuntu-20.04
steps:
- name: cancel-previous-runs
uses: styfle/cancel-workflow-action@0.9.0
with:
access_token: ${{ secrets.GITHUB_TOKEN }}
- uses: actions/checkout@v2

- name: cache-riscv
id: cache-riscv
uses: actions/cache@v2.1.6
with:
path: rv64gcv-install
key: rv64gcv-newlib-install-20210504

- name: install-riscv-build-deps
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: |
sudo apt-get update
sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev device-tree-compiler

- name: checkout-riscv-gnu-toolchain
if: steps.cache-riscv.outputs.cache-hit != 'true'
uses: actions/checkout@v2
with:
repository: riscv/riscv-gnu-toolchain
path: riscv-gnu-toolchain
ref: 28271f03bb538d926ad2889dc8ad1b0cb1b3b45c
- name: checkout-riscv-gnu-toolchain-submodules
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: |
cd riscv-gnu-toolchain
git submodule update --init --recursive --depth 1 riscv-binutils
git submodule update --init --recursive --depth 1 riscv-gcc
git submodule update --init --recursive --depth 1 riscv-glibc
git submodule update --init --recursive --depth 1 riscv-dejagnu
git submodule update --init --recursive --depth 1 riscv-newlib
git submodule update --init --recursive --depth 1 riscv-gdb
- name: riscv-gnu-toolchain
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: |
cd riscv-gnu-toolchain
sed -i '/__OBSOLETE_MATH/d' riscv-newlib/newlib/libm/common/math_errf.c
./configure --prefix=$GITHUB_WORKSPACE/rv64gcv-install --with-arch=rv64gcv_zfh
make

- name: checkout-riscv-pk
if: steps.cache-riscv.outputs.cache-hit != 'true'
uses: actions/checkout@v2
with:
repository: riscv/riscv-pk
path: riscv-pk
ref: ef7bebaf9bf24d3e90bcaae96387ce418e136b6d
- name: riscv-pk
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: |
cd riscv-pk
mkdir build
cd build
export PATH=$GITHUB_WORKSPACE/rv64gcv-install/bin:$PATH
../configure --prefix=$GITHUB_WORKSPACE/rv64gcv-install --with-arch=rv64gcv --host=riscv64-unknown-elf
make -j2
make install

- name: checkout-riscv-isa-sim
if: steps.cache-riscv.outputs.cache-hit != 'true'
uses: actions/checkout@v2
with:
repository: riscv/riscv-isa-sim
path: riscv-isa-sim
ref: 9d4f45c2ebf105503974fc80a42590ca1584c354
- name: riscv-isa-sim
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: |
cd riscv-isa-sim
mkdir build
cd build
export PATH=$GITHUB_WORKSPACE/rv64gcv-install/bin:$PATH
../configure --prefix=$GITHUB_WORKSPACE/rv64gcv-install --with-isa=rv64gcv
make -j2
make install

- name: riscv-strip-install
if: steps.cache-riscv.outputs.cache-hit != 'true'
run: find $GITHUB_WORKSPACE/rv64gcv-install -type f | xargs -i strip -g {} || true

- name: configure
run: export RISCV_ROOT_PATH=$GITHUB_WORKSPACE/rv64gcv-install && mkdir build && cd build && cmake -DCMAKE_TOOLCHAIN_FILE=../toolchains/riscv64-unknown-elf.toolchain.cmake -DNCNN_THREADS=OFF -DNCNN_OPENMP=OFF -DNCNN_BUILD_TOOLS=OFF -DNCNN_BUILD_EXAMPLES=OFF -DNCNN_BUILD_TESTS=ON ..
- name: build
run: cmake --build build -j 2
- name: test
run: |
sudo apt-get update
sudo apt-get install device-tree-compiler
export PATH=$GITHUB_WORKSPACE/rv64gcv-install/bin:$PATH
cd build
TESTS_EXECUTABLE_LOADER=spike TESTS_EXECUTABLE_LOADER_ARGUMENTS="--isa=rv64gcv_zfh;$GITHUB_WORKSPACE/rv64gcv-install/riscv64-unknown-elf/bin/pk" ctest --output-on-failure -j 2

newlib-rv64gc-gcc:
runs-on: ubuntu-20.04
steps:


+ 5
- 15
src/cpu.cpp View File

@@ -142,6 +142,7 @@ static unsigned int g_hwcaps = get_elf_hwcap_from_proc_self_auxv();

#if __riscv
// from arch/riscv/include/uapi/asm/hwcap.h
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif

@@ -412,22 +413,11 @@ int cpu_support_riscv_v()

int cpu_support_riscv_zfh()
{
#if defined __ANDROID__ || defined __linux__
#if __riscv
#if __riscv_zfh
// https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#5-discovery
__fp16 a = 0;
asm volatile(
"fneg.h %0, %0 \n"
: "=f"(a)
: "0"(a)
:);
union
{
__fp16 a;
unsigned short u;
} tmp;
tmp.a = a;
return tmp.u != 0 ? 1 : 0;
// v + f does not imply zfh, but how to discover zfh properly ?
// upstream issue https://github.com/riscv/riscv-isa-manual/issues/414
return g_hwcaps & COMPAT_HWCAP_ISA_V && g_hwcaps & COMPAT_HWCAP_ISA_F;
#else
return 0;
#endif


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