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@@ -19,7 +19,7 @@ fmla v13.4s, v16.4s, v24.s[3] |
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### practical guide |
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* use 64bit vector load only |
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* issue vector load every three fmla |
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* 1 cycle to load 64bit, dual issue with the prvious interleaved 64bit insert |
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* 1 cycle to load 64bit, dual issue with the previous interleaved 64bit insert |
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* load the remaining 64bit into integer register, dual issue with fmla |
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* update pointer, dual issue with fmla |
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* insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load |
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