Commit Graph

  • *
  • *
  • *
  • *
  • | *
  • | |\
  • * | \
  • |\ \ \
  • * | | |
  • * | | |
  • * | | |
  • | |_|/
  • |/| |
  • | * |
  • | |\ \
  • | |/ /
  • |/| |
  • * | |
  • * | |
  • | * |
  • |/ /
  • | *
  • | *
  • | *
  • | *
  • | *
  • |/
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • *
  • 51454082c Updated readme file. by Xianyi Zhang 2011-02-19 00:18:17 +0800
  • e51364edb Fixed #5 Detected Intel Westmere (using Nehalem codes) in build and dynamic arch build. Thanks Cao He from Dawning supporting Intel Xeon 5660 testbed. by Xianyi Zhang 2011-02-18 22:08:10 +0800
  • bfaa80c31 fixed #4 csrot & drot returned the wrong result when incx==incy==0 on i686 arch. by Xianyi 2011-02-18 03:00:58 +0800
  • bd7a74234 Disable quad and x precision objs in reference. by Xianyi 2011-02-18 02:50:32 +0800
  • 029d5d16d Merge branch 'master' into loongson3a by Xianyi Zhang 2011-02-17 00:39:09 +0800
  • c84315782 Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86 by Xianyi Zhang 2011-02-16 23:41:15 +0800
  • c5852d4e3 fixed #4 csrot returned the wrong result when incx==incy==0. by Xianyi Zhang 2011-02-16 23:39:43 +0800
  • c79696cc6 Added rot testcase when incx == incy ==1. by Xianyi Zhang 2011-02-16 23:32:13 +0800
  • 84ba64e65 fixed a bug in drot whe incx or incy equals to zero. by Xianyi Zhang 2011-02-16 00:18:45 +0800
  • e3e754771 Merge branch 'master' into x86 by Xianyi Zhang 2011-02-16 17:42:12 +0800
  • 1dd1bba66 Updated gitignore. by Xianyi Zhang 2011-02-16 17:37:48 +0800
  • fbf95688d Added utest frame using CUnit(http://cunit.sourceforge.net/). by Xianyi Zhang 2011-02-16 17:33:06 +0800
  • b8b27bec5 fixed a bug in drot whe incx or incy equals to zero. by Xianyi Zhang 2011-02-16 00:18:45 +0800
  • 1e671b49f Did the experiment with Loongson 3A 128bit load & store instruction. by Xianyi Zhang 2011-01-29 03:05:27 +0800
  • 77b7020d6 changed prefetch order. by Xianyi Zhang 2011-01-29 03:03:34 +0800
  • e003b811a load x & y contiguously in axpy. by Xianyi Zhang 2011-01-28 11:18:50 +0800
  • ebe2da847 Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A. by Xianyi Zhang 2011-01-27 23:07:06 +0800
  • c0b5992fa added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order. by Xianyi Zhang 2011-01-26 22:34:33 +0800
  • 376677452 Modified the unsupported instruction on Loongson3A. Closed #1 OpenBLAS could run on Loongson3A now. by Xianyi Zhang 2011-01-25 17:34:47 +0800
  • cf36f136d Updated readme for cross compiling. by Xianyi Zhang 2011-01-25 16:52:36 +0800
  • 46ce7270d fixed a typo. by Xianyi Zhang 2011-01-25 15:55:56 +0800
  • 0597c1076 Added the configures of loongson 3a. refs #1 by Xianyi Zhang 2011-01-24 22:45:35 +0000
  • 5d44a08c4 Updated readme file. by Xianyi Zhang 2011-01-24 20:03:04 +0000
  • 39aa89229 Added .gitignore files. by Xianyi Zhang 2011-01-24 19:59:52 +0000
  • 607fd78b4 Added mailing list. by Xianyi Zhang 2011-01-24 19:59:15 +0000
  • e5671535c Updated readme file. by Xianyi Zhang 2011-01-24 18:12:06 +0000
  • 066465af5 Used the environment variable OPENBLAS_NUM_THREADS to set the number of threads in test. by Xianyi Zhang 2011-01-24 18:11:35 +0000
  • e6c13e2b3 changed library name to openblas and modified environment variable. by Xianyi Zhang 2011-01-24 17:58:05 +0000
  • a8e9e1ced Added OpenBLAS docs. by Xianyi Zhang 2011-01-24 16:05:00 +0000
  • 5c9f1ebbf Fixed a bug when compiling dynamic ARCH x86 in GotoBLAS2. by Xianyi Zhang 2011-01-24 16:04:17 +0000
  • dbf3780a6 rename documents in GotoBLAS. by Xianyi Zhang 2011-01-24 15:57:23 +0000
  • 342bbc387 Import GotoBLAS2 1.13 BSD version codes. by Xianyi Zhang 2011-01-24 14:54:24 +0000