| Author | SHA1 | Message | Date |
|---|---|---|---|
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efe0b84249 |
update for riscv V extension 1.0 and arbitrary shape gemm kernels
* all modules compile with latest tools and vector extension version * easily reconfigure for different architecture preferences * reduce LMUL to avoid register spills (note LMUL=8 uses a quarter of the register bank per variable!) * multiple test fixes - corner cases (zero/negative inputs), nrm2 numeric stability * added vectorised implementations for sum/zsum |
3 years ago |