Improve the performance of rot by using AVX512 and AVX2 intrinsic

Optimize sdot/ddot for POWER10

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

Fix macro name used in ifdef for POWERPC/PGI

Changing the unroll factors for dgemm to 8 shows improved performance with
POWER10 MMA feature.   Also made some minor changes in sgemm for edge cases.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

1. Add a new API -- sbgemv to support bfloat16 based gemv
2. Implement a generic kernel for sbgemv
3. Implement an avx512-bf16 based kernel for sbgemv

Signed-off-by: Chen, Guobing <guobing.chen@intel.com>

reuse variables defined in Makefile.system

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

Increase and unify BUFFERSIZE on POWER;fix gcc inline warning

This patch makes use of new POWER10 vector pair instructions for
loads and stores. Also reorganized all variants of copy functions
to make use of same kernel.

dgemm_tcopy_16_skylakex.c CNAME function should return an int, add a
return 0 similar to other files.

As observed using GCC 10 using -march=native -ftree-vectorize
on Knights Landing, it is now smart enough to find clobbers inside
non-inlined static functions.

In particular, sgemv counted on a kernel to preserve the whole
%ymm2 register (since it was not in the clobber list), but the top
part was destroyed by vzeroupper. This caused many tests to fail.

This patch makes sure all xmm (and ymm/zmm by extension) registers
are listed as clobbered to avoid this happening, as most kernels
already did correctly in fact.

Clean up duplicate definitions in POWER8 kernels and fix power10 option passing

The
`#if defined(SKYLAKEX) || defined (COOPERLAKE)`
from that commit was before #include "common.h" so caused the
compiled function to be empty, returning garbage results for
qualifying sgemm's on those architectures.

Closes #2914

Add compiler flag for SSE4 where available

Revert special handling of Windows xNRM2 and enable C+intrinsics kern…

As the new MMA instructions need the inputs in 4x2 order for bfloat16,
changing the format in copy/packing code.  This avoids permute instructions
in the gemm kernel inner loop.

This patch fixes compilation errors due to recent renaming from SH to SB
with BUILD_BFLOAT16.

Rename "HALF" precision functions (sh prefix) to "BFLOAT16" with "sb" prefix

add fninit to reset fpu registers before assembler routines