LoongArch64 CI

Add support for LLVM Flang

Using the getauxval instruction can prevent errors
caused by hardware supporting vector instructions
while the kernel does not support them

Add (gmake) support for LLVM17's new flang

Fix ZAXPY calls with INCX=0 on pre-AVX x86_64 and add utest

Rework OpenMP thread count limit handling

Enable use of AVX512 microkernels with NVIDIA HPC from version 22.3

There are two instances when building the tests where OpenBLAS fails to
build with OpenMP and clang due to library paths getting reset as flags
are set rather than appended. This seems to only affect certain
clang/libomp installations, but if it's already grabbing the correct
library paths we might as well use them.

64-bit builds are currently broken without this flag.

Makefiles have done this already: 5720fa02c5/Makefile.system (L831)

It's defined in #4137

Use SVE zgemm/cgemm on Arm(R) Neoverse(TM) V1 core

Fix ZHEMM copy for SVE

This patch removes the prefetches from cgemm/zgemm which improves the performance similar to sgemm/dgemm did in #3868, this means I'm happy to enable this on any applicable cores.

I also replicated the unrolling the copies from sgemm and dgemm.

Whilst disambiguating whilelt, I inadvertantly used the wrong datatype
for offsets, which can be negative. This rectifies that.

Add documentation on redistributing OpenBLAS

This touches on the following:

- build configurations
- naming of symbols, shared/static libraries and other build outputs
  like pkg-config and CMake files
- (in more detail) guidance on ILP64 builds

It tries to explain that, while this is only guidance and there may be
reasons to deviate from that, for some build options there are best
practices, and for some others there are choices to make.

It also links to a number of well-maintained build recipes in order
to help packagers of other distros make choices.

Closes gh-3798

[skip ci]

Use latest non-SVE kernels in ARMV8SVE

Add ARMV8SVE to AArch64 Dynamic Dispatch

In order to enable support for future cores which have similar tunings
(in this case I'm doing this for the Arm(R) Neoverse(TM) V2 core), this generically detects SVE support and enables it. This should better manage the size and complexity of dynamic dispatch rather than just copy pasting the same parameters.

To make `ARMV8SVE` more representive of the common 128-bit SVE case,
I've split it and similar parameters from A64FX which has the wider
512-bit SVE.

These are generally better and, in some cases, include threading which helps in the cores we're targeting here.

During the last iteration of some RVV operations, accumulators can get overwritten when VL < VLMAX and tail policy is agnostic.
Commit changes intrinsics tail policy to undistrubed.