for #1664

* Support  upcoming Cannon Lake as Skylake X

This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.

My earlier PR #982 appears to have been incomplete in this regard - fixes #1285

Should fix #1109)

Add Bay Trail "Pentium N3520" atom cpu

Second part of "support Intel Avoton via Nehalem kernel"

Add recognition of Intel Atom C27xx (Avoton, model code 4D)

Conflicts:
	driver/others/memory.c

http://users.atw.hu/instlatx64/

cpuid uses register ebx, but ebx is reserved in PIC.
So save ebx, swap ebx & edi, and return edi.

Copied from Igor Pavlov's equivalent fix for 7zip (in CpuArch.c),
which is public domain and thus OK license-wise.

Signed-off-by: Timothy Gu <timothygu99@gmail.com>