OpenBLAS

Commit Graph

Author	SHA1	Message	Date
traz	a9320f896e	Fixed #25 dtrmm and dtrsm computational error on Loongson3A.	14 years ago
traz	29dce62b8f	Finish dtrsm_kernel_Rx.S on Loongson3A.	14 years ago
traz	432c309f63	Finish dtrsm_kernel_Lx.S on Loongson3A.	14 years ago
traz	d2f351d819	Modify dtrsm compiler options	14 years ago
traz	5a991b7149	Fixed #24 drmm error on Loongson3A	14 years ago
traz	9320933520	Completely dtrmm function.	15 years ago
traz	921caefa56	Increased handling trmm part, no edge handling. Test size(M and N) must be a multiple of 4 .	15 years ago
traz	ecd4c1f3d9	Modify prefetching C.	15 years ago
traz	ab9e4ce351	Adjust kc size from 112 to 116 .	15 years ago
traz	782205a693	Add dgemm compiler Options in KERNEL.LOONGSON3A.	15 years ago
traz	ac494c0d04	New kernel in LOONGSON3A.	15 years ago
Xianyi Zhang	f405b5bcc5	Fixed the bug about Loongson3A gsLQC1 & gsSQC1 instructions in daxpy kernel. Now daxpy is correct.	15 years ago
Wang Qian	d5cffd506a	Modified the default kernel makefile in MIPS64 arch.	15 years ago
Xianyi Zhang	5838f12995	Support unalign address in daxpy on loongson3a simd..	15 years ago
Xianyi Zhang	5444a3f8f7	Unroll to 16 in daxpy on loongson3a.	15 years ago
Xianyi Zhang	1e671b49f3	Did the experiment with Loongson 3A 128bit load & store instruction.	15 years ago
Xianyi Zhang	77b7020d69	changed prefetch order.	15 years ago
Xianyi Zhang	e003b811ab	load x & y contiguously in axpy.	15 years ago
Xianyi Zhang	ebe2da8474	Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A.	15 years ago
Xianyi Zhang	c0b5992fab	added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.	15 years ago
Xianyi Zhang	342bbc3871	Import GotoBLAS2 1.13 BSD version codes.	15 years ago

21 Commits (a9320f896eeea7e863dab9b300ab90bcaba0fcc3)