Add support for FP16 to openBLAS and shgemm on RISCV

Add support for Ampere AmpereOne processors

- adjust interface to disable "small matrix" pathway
- separate HFLOAT16 from BFLOAT16
- remove SHGEMM_UNROLL_M and SHGEMM_UNROLL_N equal conditions

Related to PR#5290
Co-authored-by Martin

kernel/riscv64: Fix cscal/zscal for riscv64_generic

kernel/(x86|sparc): Fix cscal and zscal by reverting to the generic C kernels

kernel/riscv64: Fix cscal and zscal

kernel/zarch: Fix cscal and zscal

kernel/power: Fixed cscal and zscal

kernel/arm64: fixed cscal and zscal

kernel/x86_64: fixed cscal and zscal

kernel/generic: Fixed cscal and zscal

kernel/riscv64:fixed the performance problem in RISCV64_ZVL256 when OPENBLAS_K is small

- modify the macro conditions in Makefile.system
- Delete development test code

Related to issue#5279

Added HFLOAT16 support for RISCV64
Added shgemm_kernel_8x8 for RISCV64_ZVL128B and shgemm_kernel_16x8 for RISCV64_ZVL256B based on HFLOAT16
The instruction sets used are ZVFH and ZFH, which need to be supported by RVV1.0

Related to issue #5279
Co-authored-by Linjin Li <linjin_li@163.com>

kernel/riscv64:Added support for omatcopy on RISCV64_ZVL256B

kernel/riscv64:Fixed the bug of openblas_utest_ext failing in c/zgemv and some c/zgbmv tests:

* Fix ARMV9SME target and add support_sme1 code for MacOS
* make sgemm_direct unconditionally available on all arm64
* build a (dummy) sgemm_direct kernel on all arm64





* Update dynamic_arm64.c

Add vector registers to clobber list to prevent compiler optimization.