Shivraj Patil
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57df7956ee
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Added CGEMM, ZGEMM, STRMM, DTRMM, CTRMM, ZTRMM. Updated macros in SGEMM, DGEMM, STRMM.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
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9 years ago |
Kaustubh Raste
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011431b9d7
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STRSM optimized for MSA
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
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9 years ago |
Kaustubh Raste
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c8a7860eb3
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STRSM optimized
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
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9 years ago |
Kaustubh Raste
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ad9f317870
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STRSM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
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9 years ago |
Shivraj Patil
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c4ba40e308
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SGEMM optimization for MIPS P5600 and I6400 using MSA. Unrolled k loop in DGEMM kernel function
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
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9 years ago |
Kaustubh Raste
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d7cbc7ac13
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DTRSM bug fix for MIPS P5600 and I6400
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
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9 years ago |
Kaustubh Raste
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edb5980c13
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DTRSM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com>
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9 years ago |
Shivraj Patil
|
b7b3d8ec8e
|
DGEMM optimization for MIPS P5600 and I6400 using MSA
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
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9 years ago |
Shivraj Patil
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2c3dfe2bf3
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MIPS P5600(32 bit) and I6400(64 bit) cores support added.
Seperated mips and mips64 files.
Configurations support for mips 32 bit.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
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9 years ago |