This patch uses vector pair pointer for input load operation
which helps to generate power10 lxvp instructions.

This patch makes use of Matrix-Multiply Assist (MMA)
feature introduced in POWER ISA v3.1 for zgemv_n and zgemv_t.

This patch makes sure that recent POWER10 patches are used
only for little endian.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

The LLVM and GCC teams agreed to rename the __builtin_mma_assemble_pair and
__builtin_mma_disassemble_pair built-ins to __builtin_vsx_assemble_pair and
__builtin_vsx_disassemble_pair respectively. This patch is to make
corresponding changes in dgemm kernel. Also made changes in
inputs to those builtins to avoid some potential typecasting issues.

Reference gcc commit id:77ef995c1fbcab76a2a69b9f4700bcfd005d8e62

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch aligns the stores to 32 byte boundary for scopy and dcopy
before entering into vector pair loop. For ccopy, changed the store
instructions to stxv to improve performance of unaligned cases.

POWER10: Improve axpy performance

This patch aligns the stores to 32 byte boundary for saxpy and daxpy
before entering into vector pair loop. Fox caxpy, changed the store
instructions to stxv to improve performance of unaligned cases.

in DTRSM and STRSM, to improve performance in Power9 and Power10.

Handling as 4x8 with vector pairs gives better performance than
existing code in POWER10.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

Changing the unroll factors for dgemm to 8 shows improved performance with
POWER10 MMA feature.   Also made some minor changes in sgemm for edge cases.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores.

This patch makes use of new POWER10 vector pair instructions for
loads and stores. Also reorganized all variants of copy functions
to make use of same kernel.

As the new MMA instructions need the inputs in 4x2 order for bfloat16,
changing the format in copy/packing code.  This avoids permute instructions
in the gemm kernel inner loop.

This patch makes use of new POWER10 vector pair instructions for
loads and stores. Tested in simulator and no new failures.

This patch makes use of new POWER10 vector pair instructions for
loads and stores. Tested in simulator and no new failures.

For the first iteration, it is better to use xvf*ger instead of xvf*gerpp
builtins which helps to avoid setting accumulators to zero. This helps
to reduce few instructions.

Making use of new vector pair POWER10 instructions in dgemv_n and dgemv_t.
Also adding a new block 4x128 to make use of Matrix-Multiply Assist (MMA)
feature introduced in POWER ISA v3.1.  Tested on simulator and there
are no new test failures.

As gcc defaults to -malign-power, removing that option. Also
adding -fno-integrated-as to use GNU assembler for powerpc
assembly optimization files. Fixed other compilation errors
reported in dgemv_t.c file.

There is a recent compiler change in __builtin_mma_disassemble_acc() which
affects the order of storing result in POWER10. Also removing new LDFLAG
-mno-power10-stub as it is handled by linker automatically.

WIP Further fixes for 32bit POWER8

Fix alignment errors in the power8 saxpy kernel