Optimize aarch64 sgemm_ncopy

replace customize bf16_to_fp32 with arm neon vcvtah_f32_bf16

Optimize gemv_n_sve kernel

Add dispatch of SBGEMVNKERNEL for NEOVERSEN2 and NEOVERSEV2

This improves performance for sbgemv_t by up to 100x on NEOVERSEV1.
The geometric mean speedup is ~61x for M=N=[2,512].

Support for SGEMM_DIRECT Kernel based on SME1

* Added ARMV9SME target
* Added SGEMM_DIRECT kernel based on SME1

LoongArch64: Fixed lapack test for LA264

When the data type is single-precision real or single-precision complex,
converting it to double precision does not prevent overflow (as exposed in LAPACK tests).
The only solution is to follow C's approach: find the maximum value in the
array and divide each element by that maximum to avoid this issue

Fixed the error when the stride is zero

Do not check whether the input parameters c and s are zero,
as this may cause errors with special values (same as scal).
Although OpenBLAS's own test suite doesn't catch this, it will
cause LAPACK test cases to fail.

Fixed incorrect store operation

Signed-off-by: gxw <guxiwei-hf@loongson.cn>

Fixed index retrieval issue when there are
identical maximum absolute values

Signed-off-by: Hao Chen <chenhao@loongson.cn>
Signed-off-by: gxw <guxiwei-hf@loongson.cn>

Fixed incorrect register usage in instructions

Signed-off-by: gxw <guxiwei-hf@loongson.cn>

Fixed register zeroing operation

Signed-off-by: Hao Chen <chenhao@loongson.cn>
Signed-off-by: gxw <guxiwei-hf@loongson.cn>

Signed-off-by: Ye Tao <ye.tao@arm.com>

Small gemm kernel improvements for AArch64

Further rearranged the rotm kernel for the different architectures.

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

* Protect align directives in assembly files that are currently problematic with LLVM on WoA

* use the armv8 zdot on WoA to work around other LLVM issues

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

"fmov.d $f2, $f4" leaves all the bits higher than the 63-th bit
unpredictable but it's obvious that the following code uses the value of
those high bits.  We actually want to replicate the lower 64 bits here,
so we should use xvreplve0.d instead.

LA464 (Loongson 3[A-Z]-5000) happens to replicate them for us due to
some uarch internal details so the issue was not detected, but for LA664
(Loongson 3[A-Z]-6000) and future uarch we need to do things correctly
or we end up getting a lot of test failures.

Closes: https://bbs.aosc.io/t/topic/302
Signed-off-by: Xi Ruoyao <xry111@xry111.site>

Replace while loop in generic C/ZGEMM_BETA to avoid going out of bounds

Optimize the omatcopy_cn/zomatcopy_cn kernels with RVV 1.0 intrinsic.