OSchip
/
OpenBLAS
Not watched
1
0
Fork 0
Code
Releases 66 Wiki evaluate Activity
Issues 0 Pull Requests 0 Datasets Model Cloudbrain HPC
48 Commits
51 Branches
78 MB
367 Download
Tree: 6eb02bbb9c
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '6eb02bbb9c'
${ noResults }
Commit Graph

12 Commits (6eb02bbb9c3d83a2081e38e40636e905f7fb6ad1)

Author SHA1 Message Date
  Xianyi Zhang 6eb02bbb9c Merge remote branch 'origin/x86' into loongson3a 15 years ago
  Xianyi 12214e1d0f Fixed #7. Modified axpy kernel codes to avoid unloop with incx==0 or incy==0 in x86 32bits arch. 15 years ago
  Xianyi Zhang 0cfd29a819 Fixed #7. 1)Disable the multi-thread and 2) Modified kernel codes to avoid unloop in axpy function when incx==0 or incy==0. 15 years ago
  Xianyi bfaa80c316 fixed #4 csrot & drot returned the wrong result when incx==incy==0 on i686 arch. 15 years ago
  Xianyi Zhang c5852d4e30 fixed #4 csrot returned the wrong result when incx==incy==0. 15 years ago
  Xianyi Zhang 84ba64e65b fixed a bug in drot whe incx or incy equals to zero. 15 years ago
  Xianyi Zhang 1e671b49f3 Did the experiment with Loongson 3A 128bit load & store instruction. 15 years ago
  Xianyi Zhang 77b7020d69 changed prefetch order. 15 years ago
  Xianyi Zhang e003b811ab load x & y contiguously in axpy. 15 years ago
  Xianyi Zhang ebe2da8474 Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A. 15 years ago
  Xianyi Zhang c0b5992fab added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order. 15 years ago
  Xianyi Zhang 342bbc3871 Import GotoBLAS2 1.13 BSD version codes. 15 years ago