2 Commits (69aa93e34f053611ed09da28862da9c22fab9b55)

Author SHA1 Message Date
  Octavian Maghiar 4a12cf53ec [RISC-V] Improve RVV kernel generator LMUL usage 2 years ago
  Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) 3 years ago