Signed-off-by: Ye Tao <ye.tao@arm.com>

Small gemm kernel improvements for AArch64

Further rearranged the rotm kernel for the different architectures.

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

* Protect align directives in assembly files that are currently problematic with LLVM on WoA

* use the armv8 zdot on WoA to work around other LLVM issues

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

"fmov.d $f2, $f4" leaves all the bits higher than the 63-th bit
unpredictable but it's obvious that the following code uses the value of
those high bits.  We actually want to replicate the lower 64 bits here,
so we should use xvreplve0.d instead.

LA464 (Loongson 3[A-Z]-5000) happens to replicate them for us due to
some uarch internal details so the issue was not detected, but for LA664
(Loongson 3[A-Z]-6000) and future uarch we need to do things correctly
or we end up getting a lot of test failures.

Closes: https://bbs.aosc.io/t/topic/302
Signed-off-by: Xi Ruoyao <xry111@xry111.site>

Replace while loop in generic C/ZGEMM_BETA to avoid going out of bounds

Optimize the omatcopy_cn/zomatcopy_cn kernels with RVV 1.0 intrinsic.

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

This reverts commit 9b9c0aa5c9.

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>

SVE Implementation for Level-1 BLAS Routines

Revert the NRM2 kernels for NeoverseN2 and ARMV8SVE targets to the generic NEON version