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10 Commits (2aab238c61044c01a0fbed438d1cf3cbb3f13d39)

Author SHA1 Message Date
  Xianyi Zhang f405b5bcc5 Fixed the bug about Loongson3A gsLQC1 & gsSQC1 instructions in daxpy kernel. Now daxpy is correct. 15 years ago
  Wang Qian d5cffd506a Modified the default kernel makefile in MIPS64 arch. 15 years ago
  Xianyi Zhang 5838f12995 Support unalign address in daxpy on loongson3a simd.. 15 years ago
  Xianyi Zhang 5444a3f8f7 Unroll to 16 in daxpy on loongson3a. 15 years ago
  Xianyi Zhang 1e671b49f3 Did the experiment with Loongson 3A 128bit load & store instruction. 15 years ago
  Xianyi Zhang 77b7020d69 changed prefetch order. 15 years ago
  Xianyi Zhang e003b811ab load x & y contiguously in axpy. 15 years ago
  Xianyi Zhang ebe2da8474 Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A. 15 years ago
  Xianyi Zhang c0b5992fab added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order. 15 years ago
  Xianyi Zhang 342bbc3871 Import GotoBLAS2 1.13 BSD version codes. 15 years ago