OpenBLAS

Commit Graph

Author	SHA1	Message	Date
Zhang Xianyi	19f17c8bc6	Merge pull request #3893 from HellerZheng/develop add riscv level3 C,Z kernel functions.	2 years ago
Sergei Lewis	9b61be4545	factoring riscv64/dot.c fix into separate PR as requested	2 years ago
Sergei Lewis	2406958629	* update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) * fix multiple numerical stability and corner case issues * add a script to generate arbitrary gemm kernel shapes * add a generic zvl256b target to demonstrate large gemm kernel unrolls	3 years ago
Heller Zheng	63cf4d0166	add riscv level3 C,Z kernel functions.	3 years ago
Xianyi Zhang	c19dff0a31	Fix T-Head RVV intrinsic API changes.	3 years ago
Heller Zheng	3918d8504e	nrm2 simple optimization	3 years ago
Heller Zheng	5d0d1c5551	Remove redundant files	3 years ago
Heller Zheng	bef47917bd	Initial version for riscv sifive x280	3 years ago
Xianyi Zhang	968e1f51d8	Update RISC-V Intrinsic API.	4 years ago
Xianyi Zhang	45786b05da	Merge branch 'develop' into risc-v	4 years ago
Wu Zhigang	92b7b949dd	fix bug in zscal function memset can not be used in zscal because of the stride parameters. Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>	4 years ago
Zhaofeng Li	590be3fae3	riscv64: Add Makefile	4 years ago
Zhaofeng Li	3521cd48cb	RISCV64_GENERIC: Use generic kernel for DSDOT for better precision The implementation in `riscv64/dot.c` fails the `test_dsdot` test, and the generic kernel seems to have better precision. Tested on SiFive FU740 (HiFive Unmatched) and QEMU. Also see #1469.	4 years ago
Zhaofeng Li	1e0192a5cc	riscv64/imin: Fix wrong comparison Same as #1990.	4 years ago
damonyu	ceb44bef14	update the intrinsic api to the offical name.	4 years ago
Xianyi Zhang	a3cac9cca0	Update sgemm kernel 1x4 for C910.	5 years ago
Xianyi Zhang	fc35b72ae1	Refs #2899 Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910	5 years ago
damonyu	ef8e7d0279	Add the support for RISC-V Vector. Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266	5 years ago
Xianyi Zhang	265ab484c8	Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc	6 years ago
Xianyi Zhang	44020a42a4	Fixed compile bug for RV64.	6 years ago
Jerry Zhao	0ee395db35	Fixed TRMM and SYMM for RISCV	7 years ago
Jerry Zhao	c167a3d6f4	Added RISCV build	7 years ago

22 Commits (19f17c8bc621973142e8d018316d5cd48fd3f4ff)