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OpenBLAS
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2558 Commits (develop)

Author SHA1 Message Date
  Xianyi Zhang c5852d4e30 fixed #4 csrot returned the wrong result when incx==incy==0. 15 years ago
  Xianyi Zhang 84ba64e65b fixed a bug in drot whe incx or incy equals to zero. 15 years ago
  Xianyi Zhang 1e671b49f3 Did the experiment with Loongson 3A 128bit load & store instruction. 15 years ago
  Xianyi Zhang 77b7020d69 changed prefetch order. 15 years ago
  Xianyi Zhang e003b811ab load x & y contiguously in axpy. 15 years ago
  Xianyi Zhang ebe2da8474 Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A. 15 years ago
  Xianyi Zhang c0b5992fab added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order. 15 years ago
  Xianyi Zhang 342bbc3871 Import GotoBLAS2 1.13 BSD version codes. 15 years ago