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Branch: develop
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12 Commits (develop)

Author SHA1 Message Date
  TGY 815cb24944 remove unused INLINE macro definitions 2 years ago
  Sergei Lewis 461ecabb22 add RISCV64_ZVL128B and RISCV64_ZVL256B targets to CI flows and to README.md 1 year ago
  kseniyazaytseva 86943afa9c Fix x280 taget include riscv_vector.h 2 years ago
  Octavian Maghiar ccbc3f875b [RISC-V] Add RISCV64_ZVL128B target to common_riscv64.h 2 years ago
  Sergei Lewis 9edb805e64 fix builds with t-head toolchains that use old versions of the intrinsics spec 2 years ago
  Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) 2 years ago
  Heller Zheng 387e8970cd Fix merge problem; Update compiling COMMON_OPT per review comments. 3 years ago
  Heller Zheng bef47917bd Initial version for riscv sifive x280 3 years ago
  Xianyi Zhang 968e1f51d8 Update RISC-V Intrinsic API. 3 years ago
  Xianyi Zhang fc35b72ae1 Refs #2899 5 years ago
  damonyu ef8e7d0279 Add the support for RISC-V Vector. 5 years ago
  Jerry Zhao c167a3d6f4 Added RISCV build 7 years ago