Martin Kroeker
GitHub
4 years ago
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 1 deletions
Unified View
Diff Options
-
+4 -1README.md
+ 4
- 1
README.md
View File
| @@ -128,6 +128,7 @@ Please read `GotoBLAS_01Readme.txt` for older CPU models already supported by th | |||||
| - **Intel Sandy Bridge**: Optimized Level-3 and Level-2 BLAS with AVX on x86-64. | - **Intel Sandy Bridge**: Optimized Level-3 and Level-2 BLAS with AVX on x86-64. | ||||
| - **Intel Haswell**: Optimized Level-3 and Level-2 BLAS with AVX2 and FMA on x86-64. | - **Intel Haswell**: Optimized Level-3 and Level-2 BLAS with AVX2 and FMA on x86-64. | ||||
| - **Intel Skylake-X**: Optimized Level-3 and Level-2 BLAS with AVX512 and FMA on x86-64. | - **Intel Skylake-X**: Optimized Level-3 and Level-2 BLAS with AVX512 and FMA on x86-64. | ||||
| - **Intel Cooper Lake**: as Skylake-X with improved BFLOAT16 support. | |||||
| - **AMD Bobcat**: Used GotoBLAS2 Barcelona codes. | - **AMD Bobcat**: Used GotoBLAS2 Barcelona codes. | ||||
| - **AMD Bulldozer**: x86-64 ?GEMM FMA4 kernels. (Thanks to Werner Saar) | - **AMD Bulldozer**: x86-64 ?GEMM FMA4 kernels. (Thanks to Werner Saar) | ||||
| - **AMD PILEDRIVER**: Uses Bulldozer codes with some optimizations. | - **AMD PILEDRIVER**: Uses Bulldozer codes with some optimizations. | ||||
| @@ -153,6 +154,7 @@ Please read `GotoBLAS_01Readme.txt` for older CPU models already supported by th | |||||
| - **ARMv8**: Basic ARMV8 with small caches, optimized Level-3 and Level-2 BLAS | - **ARMv8**: Basic ARMV8 with small caches, optimized Level-3 and Level-2 BLAS | ||||
| - **Cortex-A53**: same as ARMV8 (different cpu specifications) | - **Cortex-A53**: same as ARMV8 (different cpu specifications) | ||||
| - **Cortex-A55**: same as ARMV8 (different cpu specifications) | |||||
| - **Cortex A57**: Optimized Level-3 and Level-2 functions | - **Cortex A57**: Optimized Level-3 and Level-2 functions | ||||
| - **Cortex A72**: same as A57 ( different cpu specifications) | - **Cortex A72**: same as A57 ( different cpu specifications) | ||||
| - **Cortex A73**: same as A57 (different cpu specifications) | - **Cortex A73**: same as A57 (different cpu specifications) | ||||
| @@ -178,10 +180,11 @@ Please read `GotoBLAS_01Readme.txt` for older CPU models already supported by th | |||||
| #### RISC-V | #### RISC-V | ||||
| - **C910V**: Optimized Leve-3 BLAS (real) and Level-1,2 by RISC-V Vector extension 0.7.1. | |||||
| - **C910V**: Optimized Level-3 BLAS (real) and Level-1,2 by RISC-V Vector extension 0.7.1. | |||||
| ```sh | ```sh | ||||
| make HOSTCC=gcc TARGET=C910V CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran | make HOSTCC=gcc TARGET=C910V CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran | ||||
| ``` | ``` | ||||
| (also known to work on C906) | |||||
| ### Support for multiple targets in a single library | ### Support for multiple targets in a single library | ||||