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TargetList.txt 1.0 kB

11 years ago
11 years ago
11 years ago
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
7 years ago
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
7 years ago
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
7 years ago
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  1. Force Target Examples:
  2. make TARGET=NEHALEM
  3. make TARGET=LOONGSON3A BINARY=64
  4. make TARGET=ISTANBUL
  5. Supported List:
  6. 1.X86/X86_64
  7. a)Intel CPU:
  8. P2
  9. KATMAI
  10. COPPERMINE
  11. NORTHWOOD
  12. PRESCOTT
  13. BANIAS
  14. YONAH
  15. CORE2
  16. PENRYN
  17. DUNNINGTON
  18. NEHALEM
  19. SANDYBRIDGE
  20. HASWELL
  21. SKYLAKEX
  22. ATOM
  23. COOPERLAKE
  24. SAPPHIRERAPIDS
  25. b)AMD CPU:
  26. ATHLON
  27. OPTERON
  28. OPTERON_SSE3
  29. BARCELONA
  30. SHANGHAI
  31. ISTANBUL
  32. BOBCAT
  33. BULLDOZER
  34. PILEDRIVER
  35. STEAMROLLER
  36. EXCAVATOR
  37. ZEN
  38. c)VIA CPU:
  39. SSE_GENERIC
  40. VIAC3
  41. NANO
  42. 2.Power CPU:
  43. POWER4
  44. POWER5
  45. POWER6
  46. POWER7
  47. POWER8
  48. POWER9
  49. POWER10
  50. PPCG4
  51. PPC970
  52. PPC970MP
  53. PPC440
  54. PPC440FP2
  55. CELL
  56. 3.MIPS CPU:
  57. P5600
  58. MIPS1004K
  59. MIPS24K
  60. 4.MIPS64 CPU:
  61. SICORTEX
  62. LOONGSON3A
  63. LOONGSON3B
  64. I6400
  65. P6600
  66. I6500
  67. 5.IA64 CPU:
  68. ITANIUM2
  69. 6.SPARC CPU:
  70. SPARC
  71. SPARCV7
  72. 7.ARM CPU:
  73. CORTEXA15
  74. CORTEXA9
  75. ARMV7
  76. ARMV6
  77. ARMV5
  78. 8.ARM 64-bit CPU:
  79. ARMV8
  80. CORTEXA53
  81. CORTEXA57
  82. CORTEXA72
  83. CORTEXA73
  84. NEOVERSEN1
  85. CORTEXA55
  86. EMAG8180
  87. FALKOR
  88. THUNDERX
  89. THUNDERX2T99
  90. TSV110
  91. THUNDERX3T110
  92. VORTEX
  93. 9.System Z:
  94. ZARCH_GENERIC
  95. Z13
  96. Z14
  97. 10.RISC-V 64:
  98. RISCV64_GENERIC
  99. C910V
  100. 11.LOONGARCH64:
  101. LOONGSON3R5