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ztrsm_kernel_cell_LT.S 39 kB

rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
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  1. /*********************************************************************/
  2. /* Copyright 2009, 2010 The University of Texas at Austin. */
  3. /* All rights reserved. */
  4. /* */
  5. /* Redistribution and use in source and binary forms, with or */
  6. /* without modification, are permitted provided that the following */
  7. /* conditions are met: */
  8. /* */
  9. /* 1. Redistributions of source code must retain the above */
  10. /* copyright notice, this list of conditions and the following */
  11. /* disclaimer. */
  12. /* */
  13. /* 2. Redistributions in binary form must reproduce the above */
  14. /* copyright notice, this list of conditions and the following */
  15. /* disclaimer in the documentation and/or other materials */
  16. /* provided with the distribution. */
  17. /* */
  18. /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
  19. /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
  20. /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
  21. /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
  22. /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
  23. /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
  24. /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
  25. /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
  26. /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
  27. /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
  28. /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
  29. /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
  30. /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
  31. /* POSSIBILITY OF SUCH DAMAGE. */
  32. /* */
  33. /* The views and conclusions contained in the software and */
  34. /* documentation are those of the authors and should not be */
  35. /* interpreted as representing official policies, either expressed */
  36. /* or implied, of The University of Texas at Austin. */
  37. /*********************************************************************/
  38. #define ASSEMBLER
  39. #include "common.h"
  40. #ifndef __64BIT__
  41. #define LOAD lwz
  42. #else
  43. #define LOAD ld
  44. #endif
  45. #ifdef __64BIT__
  46. #define STACKSIZE 320
  47. #define ALPHA_R 296(SP)
  48. #define ALPHA_I 304(SP)
  49. #define FZERO 312(SP)
  50. #else
  51. #define STACKSIZE 256
  52. #define ALPHA_R 224(SP)
  53. #define ALPHA_I 232(SP)
  54. #define FZERO 240(SP)
  55. #endif
  56. #define M r3
  57. #define N r4
  58. #define K r5
  59. #if defined(linux) || defined(__FreeBSD__)
  60. #ifndef __64BIT__
  61. #define A r6
  62. #define B r7
  63. #define C r8
  64. #define LDC r9
  65. #define OFFSET r10
  66. #else
  67. #define A r8
  68. #define B r9
  69. #define C r10
  70. #define LDC r6
  71. #define OFFSET r7
  72. #endif
  73. #endif
  74. #if defined(_AIX) || defined(__APPLE__)
  75. #if !defined(__64BIT__) && defined(DOUBLE)
  76. #define A r10
  77. #define B r6
  78. #define C r7
  79. #define LDC r8
  80. #define OFFSET r9
  81. #else
  82. #define A r8
  83. #define B r9
  84. #define C r10
  85. #define LDC r6
  86. #define OFFSET r7
  87. #endif
  88. #endif
  89. #define AORIG r21
  90. #define TEMP r22
  91. #define KK r23
  92. #define I r24
  93. #define J r25
  94. #define AO r26
  95. #define BO r27
  96. #define CO1 r28
  97. #define CO2 r29
  98. #define PREA r30
  99. #define PREC r31
  100. #define PREB PREA
  101. #ifndef NEEDPARAM
  102. #ifndef DOUBLE
  103. #include "cparam.h"
  104. #else
  105. #include "zparam.h"
  106. #endif
  107. PROLOGUE
  108. PROFCODE
  109. addi SP, SP, -STACKSIZE
  110. li r0, 0
  111. stfd f14, 0(SP)
  112. stfd f15, 8(SP)
  113. stfd f16, 16(SP)
  114. stfd f17, 24(SP)
  115. stfd f18, 32(SP)
  116. stfd f19, 40(SP)
  117. stfd f20, 48(SP)
  118. stfd f21, 56(SP)
  119. stfd f22, 64(SP)
  120. stfd f23, 72(SP)
  121. stfd f24, 80(SP)
  122. stfd f25, 88(SP)
  123. stfd f26, 96(SP)
  124. stfd f27, 104(SP)
  125. stfd f28, 112(SP)
  126. stfd f29, 120(SP)
  127. stfd f30, 128(SP)
  128. stfd f31, 136(SP)
  129. #ifdef __64BIT__
  130. std r31, 144(SP)
  131. std r30, 152(SP)
  132. std r29, 160(SP)
  133. std r28, 168(SP)
  134. std r27, 176(SP)
  135. std r26, 184(SP)
  136. std r25, 192(SP)
  137. std r24, 200(SP)
  138. std r23, 208(SP)
  139. std r22, 216(SP)
  140. std r21, 224(SP)
  141. #else
  142. stw r31, 144(SP)
  143. stw r30, 148(SP)
  144. stw r29, 152(SP)
  145. stw r28, 156(SP)
  146. stw r27, 160(SP)
  147. stw r26, 164(SP)
  148. stw r25, 168(SP)
  149. stw r24, 172(SP)
  150. stw r23, 176(SP)
  151. stw r22, 180(SP)
  152. stw r21, 184(SP)
  153. #endif
  154. stw r0, FZERO
  155. #if defined(linux) || defined(__FreeBSD__)
  156. #ifdef __64BIT__
  157. ld LDC, FRAMESLOT(0) + STACKSIZE(SP)
  158. #endif
  159. #endif
  160. #if defined(_AIX) || defined(__APPLE__)
  161. #ifdef __64BIT__
  162. ld LDC, FRAMESLOT(0) + STACKSIZE(SP)
  163. #else
  164. #ifdef DOUBLE
  165. lwz B, FRAMESLOT(0) + STACKSIZE(SP)
  166. lwz C, FRAMESLOT(1) + STACKSIZE(SP)
  167. lwz LDC, FRAMESLOT(2) + STACKSIZE(SP)
  168. #else
  169. lwz LDC, FRAMESLOT(0) + STACKSIZE(SP)
  170. #endif
  171. #endif
  172. #endif
  173. #if (defined(linux) || defined(__FreeBSD__)) && defined(__64BIT__)
  174. ld OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  175. #endif
  176. #if defined(_AIX) || defined(__APPLE__)
  177. #ifdef __64BIT__
  178. ld OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  179. #else
  180. #ifdef DOUBLE
  181. lwz OFFSET, FRAMESLOT(3) + STACKSIZE(SP)
  182. #else
  183. lwz OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  184. #endif
  185. #endif
  186. #endif
  187. slwi LDC, LDC, ZBASE_SHIFT
  188. #ifdef LN
  189. mullw r0, M, K
  190. slwi r0, r0, ZBASE_SHIFT
  191. add A, A, r0
  192. slwi r0, M, ZBASE_SHIFT
  193. add C, C, r0
  194. #endif
  195. #ifdef RN
  196. neg KK, OFFSET
  197. #endif
  198. #ifdef RT
  199. mullw r0, N, K
  200. slwi r0, r0, ZBASE_SHIFT
  201. add B, B, r0
  202. mullw r0, N, LDC
  203. add C, C, r0
  204. sub KK, N, OFFSET
  205. #endif
  206. cmpwi cr0, M, 0
  207. ble LL(999)
  208. cmpwi cr0, N, 0
  209. ble LL(999)
  210. cmpwi cr0, K, 0
  211. ble LL(999)
  212. #ifndef PREFETCHTEST
  213. li PREC, 3 * SIZE
  214. li PREA, 16 * 12 * SIZE
  215. #else
  216. #if defined(linux) || defined(__FreeBSD__)
  217. #ifndef __64BIT__
  218. lwz PREA, FRAMESLOT(2) + STACKSIZE(SP)
  219. lwz PREC, FRAMESLOT(3) + STACKSIZE(SP)
  220. #else
  221. ld PREA, FRAMESLOT(3) + STACKSIZE(SP)
  222. ld PREC, FRAMESLOT(4) + STACKSIZE(SP)
  223. #endif
  224. #endif
  225. #if defined(_AIX) || defined(__APPLE__)
  226. #ifdef __64BIT__
  227. ld PREA, FRAMESLOT(3) + STACKSIZE(SP)
  228. ld PREC, FRAMESLOT(4) + STACKSIZE(SP)
  229. #else
  230. #ifdef DOUBLE
  231. lwz PREA, FRAMESLOT(4) + STACKSIZE(SP)
  232. lwz PREC, FRAMESLOT(5) + STACKSIZE(SP)
  233. #else
  234. lwz PREA, FRAMESLOT(3) + STACKSIZE(SP)
  235. lwz PREC, FRAMESLOT(4) + STACKSIZE(SP)
  236. #endif
  237. #endif
  238. #endif
  239. #endif
  240. srawi. J, N, 1
  241. ble LL(30)
  242. .align 4
  243. LL(10):
  244. #ifdef RT
  245. slwi r0, K, 1 + ZBASE_SHIFT
  246. sub B, B, r0
  247. slwi r0, LDC, 1
  248. sub C, C, r0
  249. #endif
  250. mr CO1, C
  251. add CO2, C, LDC
  252. #ifdef LN
  253. add KK, M, OFFSET
  254. #endif
  255. #ifdef LT
  256. mr KK, OFFSET
  257. #endif
  258. srawi. I, M, 1
  259. #if defined(LN) || defined(RT)
  260. mr AORIG, A
  261. #else
  262. mr AO, A
  263. #endif
  264. #ifndef RT
  265. add C, CO2, LDC
  266. #endif
  267. ble LL(20)
  268. .align 4
  269. LL(11):
  270. #if defined(LT) || defined(RN)
  271. LFD f16, 0 * SIZE(AO)
  272. LFD f17, 1 * SIZE(AO)
  273. LFD f18, 2 * SIZE(AO)
  274. LFD f19, 3 * SIZE(AO)
  275. LFD f20, 0 * SIZE(B)
  276. LFD f21, 1 * SIZE(B)
  277. LFD f22, 2 * SIZE(B)
  278. LFD f23, 3 * SIZE(B)
  279. LFD f24, 4 * SIZE(AO)
  280. LFD f25, 5 * SIZE(AO)
  281. LFD f26, 6 * SIZE(AO)
  282. LFD f28, 4 * SIZE(B)
  283. LFD f29, 5 * SIZE(B)
  284. LFD f30, 6 * SIZE(B)
  285. lfs f0, FZERO
  286. fmr f1, f0
  287. fmr f2, f0
  288. fmr f3, f0
  289. fmr f4, f0
  290. fmr f5, f0
  291. fmr f6, f0
  292. fmr f7, f0
  293. fmr f8, f0
  294. fmr f9, f0
  295. fmr f10, f0
  296. fmr f11, f0
  297. fmr f12, f0
  298. fmr f13, f0
  299. fmr f14, f0
  300. fmr f15, f0
  301. dcbt CO1, PREC
  302. dcbt CO2, PREC
  303. srawi. r0, KK, 2
  304. mtspr CTR, r0
  305. mr BO, B
  306. #else
  307. #ifdef LN
  308. slwi r0, K, 1 + ZBASE_SHIFT
  309. sub AORIG, AORIG, r0
  310. #endif
  311. slwi TEMP, KK, 1 + ZBASE_SHIFT
  312. add AO, AORIG, TEMP
  313. add BO, B, TEMP
  314. sub TEMP, K, KK
  315. LFD f16, 0 * SIZE(AO)
  316. LFD f17, 1 * SIZE(AO)
  317. LFD f18, 2 * SIZE(AO)
  318. LFD f19, 3 * SIZE(AO)
  319. LFD f20, 0 * SIZE(BO)
  320. LFD f21, 1 * SIZE(BO)
  321. LFD f22, 2 * SIZE(BO)
  322. LFD f23, 3 * SIZE(BO)
  323. lfs f0, FZERO
  324. fmr f1, f0
  325. fmr f2, f0
  326. fmr f3, f0
  327. fmr f4, f0
  328. fmr f5, f0
  329. fmr f6, f0
  330. fmr f7, f0
  331. fmr f8, f0
  332. fmr f9, f0
  333. fmr f10, f0
  334. fmr f11, f0
  335. fmr f12, f0
  336. fmr f13, f0
  337. fmr f14, f0
  338. fmr f15, f0
  339. dcbt CO1, PREC
  340. dcbt CO2, PREC
  341. srawi. r0, TEMP, 2
  342. mtspr CTR, r0
  343. #endif
  344. ble LL(15)
  345. .align 4
  346. #define NOP1 mr r18, r18
  347. #define NOP2 mr r19, r19
  348. LL(12):
  349. FMADD f0, f16, f20, f0
  350. dcbt AO, PREA
  351. FMADD f4, f16, f21, f4
  352. dcbt BO, PREB
  353. FMADD f8, f16, f22, f8
  354. LFD f31, 7 * SIZE(BO)
  355. FMADD f12, f16, f23, f12
  356. LFD f27, 7 * SIZE(AO)
  357. FMADD f1, f17, f20, f1
  358. LFD f16, 8 * SIZE(AO)
  359. FMADD f5, f17, f21, f5
  360. NOP2
  361. FMADD f9, f17, f22, f9
  362. NOP1
  363. FMADD f13, f17, f23, f13
  364. LFD f17, 9 * SIZE(AO)
  365. FMADD f2, f18, f20, f2
  366. NOP1
  367. FMADD f6, f18, f21, f6
  368. NOP2
  369. FMADD f10, f18, f22, f10
  370. NOP1
  371. FMADD f14, f18, f23, f14
  372. LFD f18, 10 * SIZE(AO)
  373. FMADD f3, f19, f20, f3
  374. LFD f20, 8 * SIZE(BO)
  375. FMADD f7, f19, f21, f7
  376. LFD f21, 9 * SIZE(BO)
  377. FMADD f11, f19, f22, f11
  378. LFD f22, 10 * SIZE(BO)
  379. FMADD f15, f19, f23, f15
  380. LFD f19, 11 * SIZE(AO)
  381. FMADD f0, f24, f28, f0
  382. LFD f23, 11 * SIZE(BO)
  383. FMADD f4, f24, f29, f4
  384. NOP2
  385. FMADD f8, f24, f30, f8
  386. NOP1
  387. FMADD f12, f24, f31, f12
  388. LFD f24, 12 * SIZE(AO)
  389. FMADD f1, f25, f28, f1
  390. NOP1
  391. FMADD f5, f25, f29, f5
  392. NOP2
  393. FMADD f9, f25, f30, f9
  394. NOP1
  395. FMADD f13, f25, f31, f13
  396. LFD f25, 13 * SIZE(AO)
  397. FMADD f2, f26, f28, f2
  398. NOP1
  399. FMADD f6, f26, f29, f6
  400. NOP2
  401. FMADD f10, f26, f30, f10
  402. NOP1
  403. FMADD f14, f26, f31, f14
  404. LFD f26, 14 * SIZE(AO)
  405. FMADD f3, f27, f28, f3
  406. LFD f28, 12 * SIZE(BO)
  407. FMADD f7, f27, f29, f7
  408. LFD f29, 13 * SIZE(BO)
  409. FMADD f11, f27, f30, f11
  410. LFD f30, 14 * SIZE(BO)
  411. FMADD f15, f27, f31, f15
  412. LFD f27, 15 * SIZE(AO)
  413. FMADD f0, f16, f20, f0
  414. LFD f31, 15 * SIZE(BO)
  415. FMADD f4, f16, f21, f4
  416. NOP2
  417. FMADD f8, f16, f22, f8
  418. NOP1
  419. FMADD f12, f16, f23, f12
  420. LFD f16, 16 * SIZE(AO)
  421. FMADD f1, f17, f20, f1
  422. NOP1
  423. FMADD f5, f17, f21, f5
  424. NOP2
  425. FMADD f9, f17, f22, f9
  426. NOP1
  427. FMADD f13, f17, f23, f13
  428. LFD f17, 17 * SIZE(AO)
  429. FMADD f2, f18, f20, f2
  430. NOP1
  431. FMADD f6, f18, f21, f6
  432. NOP2
  433. FMADD f10, f18, f22, f10
  434. NOP1
  435. FMADD f14, f18, f23, f14
  436. LFD f18, 18 * SIZE(AO)
  437. FMADD f3, f19, f20, f3
  438. LFD f20, 16 * SIZE(BO)
  439. FMADD f7, f19, f21, f7
  440. LFD f21, 17 * SIZE(BO)
  441. FMADD f11, f19, f22, f11
  442. LFD f22, 18 * SIZE(BO)
  443. FMADD f15, f19, f23, f15
  444. LFD f19, 19 * SIZE(AO)
  445. FMADD f0, f24, f28, f0
  446. LFD f23, 19 * SIZE(BO)
  447. FMADD f4, f24, f29, f4
  448. NOP2
  449. FMADD f8, f24, f30, f8
  450. NOP1
  451. FMADD f12, f24, f31, f12
  452. LFD f24, 20 * SIZE(AO)
  453. FMADD f1, f25, f28, f1
  454. NOP1
  455. FMADD f5, f25, f29, f5
  456. NOP2
  457. FMADD f9, f25, f30, f9
  458. NOP1
  459. FMADD f13, f25, f31, f13
  460. LFD f25, 21 * SIZE(AO)
  461. FMADD f2, f26, f28, f2
  462. NOP1
  463. FMADD f6, f26, f29, f6
  464. NOP2
  465. FMADD f10, f26, f30, f10
  466. NOP1
  467. FMADD f14, f26, f31, f14
  468. LFD f26, 22 * SIZE(AO)
  469. FMADD f3, f27, f28, f3
  470. LFD f28, 20 * SIZE(BO)
  471. FMADD f7, f27, f29, f7
  472. LFD f29, 21 * SIZE(BO)
  473. FMADD f11, f27, f30, f11
  474. LFD f30, 22 * SIZE(BO)
  475. FMADD f15, f27, f31, f15
  476. addi AO, AO, 16 * SIZE
  477. addi BO, BO, 16 * SIZE
  478. bdnz LL(12)
  479. .align 4
  480. LL(15):
  481. #if defined(LT) || defined(RN)
  482. andi. r0, KK, 3
  483. #else
  484. andi. r0, TEMP, 3
  485. #endif
  486. mtspr CTR, r0
  487. ble LL(KERNEL_MainFinish)
  488. .align 4
  489. LL(16):
  490. fmadd f0, f16, f20, f0
  491. fmadd f5, f17, f21, f5
  492. fmadd f10, f18, f22, f10
  493. fmadd f15, f19, f23, f15
  494. fmadd f1, f17, f20, f1
  495. fmadd f2, f18, f20, f2
  496. fmadd f3, f19, f20, f3
  497. fmadd f4, f16, f21, f4
  498. fmadd f6, f18, f21, f6
  499. fmadd f7, f19, f21, f7
  500. fmadd f8, f16, f22, f8
  501. fmadd f9, f17, f22, f9
  502. fmadd f11, f19, f22, f11
  503. fmadd f12, f16, f23, f12
  504. fmadd f13, f17, f23, f13
  505. fmadd f14, f18, f23, f14
  506. LFD f16, 4 * SIZE(AO)
  507. LFD f17, 5 * SIZE(AO)
  508. LFD f18, 6 * SIZE(AO)
  509. LFD f19, 7 * SIZE(AO)
  510. LFD f20, 4 * SIZE(BO)
  511. LFD f21, 5 * SIZE(BO)
  512. LFD f22, 6 * SIZE(BO)
  513. LFD f23, 7 * SIZE(BO)
  514. addi BO, BO, 4 * SIZE
  515. addi AO, AO, 4 * SIZE
  516. bdnz LL(16)
  517. .align 4
  518. LL(KERNEL_MainFinish):
  519. #ifndef CONJ
  520. FSUB f0, f0, f5
  521. FADD f1, f1, f4
  522. FSUB f2, f2, f7
  523. FADD f3, f3, f6
  524. FSUB f8, f8, f13
  525. FADD f9, f9, f12
  526. FSUB f10, f10, f15
  527. FADD f11, f11, f14
  528. #else
  529. FADD f0, f0, f5
  530. FSUB f1, f4, f1
  531. FADD f2, f2, f7
  532. FSUB f3, f6, f3
  533. FADD f8, f8, f13
  534. FSUB f9, f12, f9
  535. FADD f10, f10, f15
  536. FSUB f11, f14, f11
  537. #endif
  538. #if defined(LN) || defined(RT)
  539. subi r0, KK, 2
  540. slwi r0, r0, 1 + ZBASE_SHIFT
  541. add AO, AORIG, r0
  542. add BO, B, r0
  543. #endif
  544. #if defined(LN) || defined(LT)
  545. LFD f16, 0 * SIZE(BO)
  546. LFD f17, 1 * SIZE(BO)
  547. LFD f18, 2 * SIZE(BO)
  548. LFD f19, 3 * SIZE(BO)
  549. LFD f20, 4 * SIZE(BO)
  550. LFD f21, 5 * SIZE(BO)
  551. LFD f22, 6 * SIZE(BO)
  552. LFD f23, 7 * SIZE(BO)
  553. FSUB f0, f16, f0
  554. FSUB f1, f17, f1
  555. FSUB f8, f18, f8
  556. FSUB f9, f19, f9
  557. FSUB f2, f20, f2
  558. FSUB f3, f21, f3
  559. FSUB f10, f22, f10
  560. FSUB f11, f23, f11
  561. #else
  562. LFD f16, 0 * SIZE(AO)
  563. LFD f17, 1 * SIZE(AO)
  564. LFD f18, 2 * SIZE(AO)
  565. LFD f19, 3 * SIZE(AO)
  566. LFD f20, 4 * SIZE(AO)
  567. LFD f21, 5 * SIZE(AO)
  568. LFD f22, 6 * SIZE(AO)
  569. LFD f23, 7 * SIZE(AO)
  570. #ifndef CONJ
  571. FSUB f0, f16, f0
  572. FSUB f1, f17, f1
  573. FSUB f2, f18, f2
  574. FSUB f3, f19, f3
  575. FSUB f8, f20, f8
  576. FSUB f9, f21, f9
  577. FSUB f10, f22, f10
  578. FSUB f11, f23, f11
  579. #else
  580. FSUB f0, f16, f0
  581. FADD f1, f17, f1
  582. FSUB f2, f18, f2
  583. FADD f3, f19, f3
  584. FSUB f8, f20, f8
  585. FADD f9, f21, f9
  586. FSUB f10, f22, f10
  587. FADD f11, f23, f11
  588. #endif
  589. #endif
  590. #ifdef LN
  591. LFD f16, 6 * SIZE(AO)
  592. LFD f17, 7 * SIZE(AO)
  593. LFD f18, 4 * SIZE(AO)
  594. LFD f19, 5 * SIZE(AO)
  595. LFD f20, 0 * SIZE(AO)
  596. LFD f21, 1 * SIZE(AO)
  597. FMUL f6, f17, f3
  598. FMUL f7, f17, f2
  599. FMUL f14, f17, f11
  600. FMUL f15, f17, f10
  601. #ifndef CONJ
  602. FMSUB f2, f16, f2, f6
  603. FMADD f3, f16, f3, f7
  604. FMSUB f10, f16, f10, f14
  605. FMADD f11, f16, f11, f15
  606. FMADD f0, f19, f3, f0
  607. FNMSUB f1, f19, f2, f1
  608. FMADD f8, f19, f11, f8
  609. FNMSUB f9, f19, f10, f9
  610. FNMSUB f0, f18, f2, f0
  611. FNMSUB f1, f18, f3, f1
  612. FNMSUB f8, f18, f10, f8
  613. FNMSUB f9, f18, f11, f9
  614. FMUL f4, f21, f1
  615. FMUL f5, f21, f0
  616. FMUL f12, f21, f9
  617. FMUL f13, f21, f8
  618. FMSUB f0, f20, f0, f4
  619. FMADD f1, f20, f1, f5
  620. FMSUB f8, f20, f8, f12
  621. FMADD f9, f20, f9, f13
  622. #else
  623. FMADD f2, f16, f2, f6
  624. FMSUB f3, f16, f3, f7
  625. FMADD f10, f16, f10, f14
  626. FMSUB f11, f16, f11, f15
  627. FMSUB f0, f19, f3, f0
  628. FNMADD f1, f19, f2, f1
  629. FMSUB f8, f19, f11, f8
  630. FNMADD f9, f19, f10, f9
  631. FNMADD f0, f18, f2, f0
  632. FNMADD f1, f18, f3, f1
  633. FNMADD f8, f18, f10, f8
  634. FNMADD f9, f18, f11, f9
  635. FMUL f4, f21, f1
  636. FMUL f5, f21, f0
  637. FMUL f12, f21, f9
  638. FMUL f13, f21, f8
  639. FMADD f0, f20, f0, f4
  640. FMSUB f1, f20, f1, f5
  641. FMADD f8, f20, f8, f12
  642. FMSUB f9, f20, f9, f13
  643. #endif
  644. #endif
  645. #ifdef LT
  646. LFD f16, 0 * SIZE(AO)
  647. LFD f17, 1 * SIZE(AO)
  648. LFD f18, 2 * SIZE(AO)
  649. LFD f19, 3 * SIZE(AO)
  650. LFD f20, 6 * SIZE(AO)
  651. LFD f21, 7 * SIZE(AO)
  652. FMUL f4, f17, f1
  653. FMUL f5, f17, f0
  654. FMUL f12, f17, f9
  655. FMUL f13, f17, f8
  656. #ifndef CONJ
  657. FMSUB f0, f16, f0, f4
  658. FMADD f1, f16, f1, f5
  659. FMSUB f8, f16, f8, f12
  660. FMADD f9, f16, f9, f13
  661. FMADD f2, f19, f1, f2
  662. FNMSUB f3, f19, f0, f3
  663. FMADD f10, f19, f9, f10
  664. FNMSUB f11, f19, f8, f11
  665. FNMSUB f2, f18, f0, f2
  666. FNMSUB f3, f18, f1, f3
  667. FNMSUB f10, f18, f8, f10
  668. FNMSUB f11, f18, f9, f11
  669. FMUL f4, f21, f3
  670. FMUL f5, f21, f2
  671. FMUL f12, f21, f11
  672. FMUL f13, f21, f10
  673. FMSUB f2, f20, f2, f4
  674. FMADD f3, f20, f3, f5
  675. FMSUB f10, f20, f10, f12
  676. FMADD f11, f20, f11, f13
  677. #else
  678. FMADD f0, f16, f0, f4
  679. FMSUB f1, f16, f1, f5
  680. FMADD f8, f16, f8, f12
  681. FMSUB f9, f16, f9, f13
  682. FMSUB f2, f19, f1, f2
  683. FNMADD f3, f19, f0, f3
  684. FMSUB f10, f19, f9, f10
  685. FNMADD f11, f19, f8, f11
  686. FNMADD f2, f18, f0, f2
  687. FNMADD f3, f18, f1, f3
  688. FNMADD f10, f18, f8, f10
  689. FNMADD f11, f18, f9, f11
  690. FMUL f4, f21, f3
  691. FMUL f5, f21, f2
  692. FMUL f12, f21, f11
  693. FMUL f13, f21, f10
  694. FMADD f2, f20, f2, f4
  695. FMSUB f3, f20, f3, f5
  696. FMADD f10, f20, f10, f12
  697. FMSUB f11, f20, f11, f13
  698. #endif
  699. #endif
  700. #ifdef RN
  701. LFD f16, 0 * SIZE(BO)
  702. LFD f17, 1 * SIZE(BO)
  703. LFD f18, 2 * SIZE(BO)
  704. LFD f19, 3 * SIZE(BO)
  705. LFD f20, 6 * SIZE(BO)
  706. LFD f21, 7 * SIZE(BO)
  707. FMUL f4, f17, f1
  708. FMUL f5, f17, f0
  709. FMUL f6, f17, f3
  710. FMUL f7, f17, f2
  711. #ifndef CONJ
  712. FMSUB f0, f16, f0, f4
  713. FMADD f1, f16, f1, f5
  714. FMSUB f2, f16, f2, f6
  715. FMADD f3, f16, f3, f7
  716. FMADD f8, f19, f1, f8
  717. FNMSUB f9, f19, f0, f9
  718. FMADD f10, f19, f3, f10
  719. FNMSUB f11, f19, f2, f11
  720. FNMSUB f8, f18, f0, f8
  721. FNMSUB f9, f18, f1, f9
  722. FNMSUB f10, f18, f2, f10
  723. FNMSUB f11, f18, f3, f11
  724. FMUL f4, f21, f9
  725. FMUL f5, f21, f8
  726. FMUL f6, f21, f11
  727. FMUL f7, f21, f10
  728. FMSUB f8, f20, f8, f4
  729. FMADD f9, f20, f9, f5
  730. FMSUB f10, f20, f10, f6
  731. FMADD f11, f20, f11, f7
  732. #else
  733. FMADD f0, f16, f0, f4
  734. FMSUB f1, f16, f1, f5
  735. FMADD f2, f16, f2, f6
  736. FMSUB f3, f16, f3, f7
  737. FMSUB f8, f19, f1, f8
  738. FNMADD f9, f19, f0, f9
  739. FMSUB f10, f19, f3, f10
  740. FNMADD f11, f19, f2, f11
  741. FNMADD f8, f18, f0, f8
  742. FNMADD f9, f18, f1, f9
  743. FNMADD f10, f18, f2, f10
  744. FNMADD f11, f18, f3, f11
  745. FMUL f4, f21, f9
  746. FMUL f5, f21, f8
  747. FMUL f6, f21, f11
  748. FMUL f7, f21, f10
  749. FMADD f8, f20, f8, f4
  750. FMSUB f9, f20, f9, f5
  751. FMADD f10, f20, f10, f6
  752. FMSUB f11, f20, f11, f7
  753. #endif
  754. #endif
  755. #ifdef RT
  756. LFD f16, 6 * SIZE(BO)
  757. LFD f17, 7 * SIZE(BO)
  758. LFD f18, 4 * SIZE(BO)
  759. LFD f19, 5 * SIZE(BO)
  760. LFD f20, 0 * SIZE(BO)
  761. LFD f21, 1 * SIZE(BO)
  762. FMUL f12, f17, f9
  763. FMUL f13, f17, f8
  764. FMUL f14, f17, f11
  765. FMUL f15, f17, f10
  766. #ifndef CONJ
  767. FMSUB f8, f16, f8, f12
  768. FMADD f9, f16, f9, f13
  769. FMSUB f10, f16, f10, f14
  770. FMADD f11, f16, f11, f15
  771. FMADD f0, f19, f9, f0
  772. FNMSUB f1, f19, f8, f1
  773. FMADD f2, f19, f11, f2
  774. FNMSUB f3, f19, f10, f3
  775. FNMSUB f0, f18, f8, f0
  776. FNMSUB f1, f18, f9, f1
  777. FNMSUB f2, f18, f10, f2
  778. FNMSUB f3, f18, f11, f3
  779. FMUL f4, f21, f1
  780. FMUL f5, f21, f0
  781. FMUL f6, f21, f3
  782. FMUL f7, f21, f2
  783. FMSUB f0, f20, f0, f4
  784. FMADD f1, f20, f1, f5
  785. FMSUB f2, f20, f2, f6
  786. FMADD f3, f20, f3, f7
  787. #else
  788. FMADD f8, f16, f8, f12
  789. FMSUB f9, f16, f9, f13
  790. FMADD f10, f16, f10, f14
  791. FMSUB f11, f16, f11, f15
  792. FMSUB f0, f19, f9, f0
  793. FNMADD f1, f19, f8, f1
  794. FMSUB f2, f19, f11, f2
  795. FNMADD f3, f19, f10, f3
  796. FNMADD f0, f18, f8, f0
  797. FNMADD f1, f18, f9, f1
  798. FNMADD f2, f18, f10, f2
  799. FNMADD f3, f18, f11, f3
  800. FMUL f4, f21, f1
  801. FMUL f5, f21, f0
  802. FMUL f6, f21, f3
  803. FMUL f7, f21, f2
  804. FMADD f0, f20, f0, f4
  805. FMSUB f1, f20, f1, f5
  806. FMADD f2, f20, f2, f6
  807. FMSUB f3, f20, f3, f7
  808. #endif
  809. #endif
  810. #ifdef LN
  811. subi CO1, CO1, 4 * SIZE
  812. subi CO2, CO2, 4 * SIZE
  813. #endif
  814. #if defined(LN) || defined(LT)
  815. STFD f0, 0 * SIZE(BO)
  816. STFD f1, 1 * SIZE(BO)
  817. STFD f8, 2 * SIZE(BO)
  818. STFD f9, 3 * SIZE(BO)
  819. STFD f2, 4 * SIZE(BO)
  820. STFD f3, 5 * SIZE(BO)
  821. STFD f10, 6 * SIZE(BO)
  822. STFD f11, 7 * SIZE(BO)
  823. #else
  824. STFD f0, 0 * SIZE(AO)
  825. STFD f1, 1 * SIZE(AO)
  826. STFD f2, 2 * SIZE(AO)
  827. STFD f3, 3 * SIZE(AO)
  828. STFD f8, 4 * SIZE(AO)
  829. STFD f9, 5 * SIZE(AO)
  830. STFD f10, 6 * SIZE(AO)
  831. STFD f11, 7 * SIZE(AO)
  832. #endif
  833. STFD f0, 0 * SIZE(CO1)
  834. STFD f1, 1 * SIZE(CO1)
  835. STFD f2, 2 * SIZE(CO1)
  836. STFD f3, 3 * SIZE(CO1)
  837. STFD f8, 0 * SIZE(CO2)
  838. STFD f9, 1 * SIZE(CO2)
  839. STFD f10, 2 * SIZE(CO2)
  840. STFD f11, 3 * SIZE(CO2)
  841. #ifndef LN
  842. addi CO1, CO1, 4 * SIZE
  843. addi CO2, CO2, 4 * SIZE
  844. #endif
  845. #ifdef RT
  846. slwi r0, K, 1 + ZBASE_SHIFT
  847. add AORIG, AORIG, r0
  848. #endif
  849. #if defined(LT) || defined(RN)
  850. sub TEMP, K, KK
  851. slwi TEMP, TEMP, 1 + ZBASE_SHIFT
  852. add AO, AO, TEMP
  853. add BO, BO, TEMP
  854. #endif
  855. #ifdef LT
  856. addi KK, KK, 2
  857. #endif
  858. #ifdef LN
  859. subi KK, KK, 2
  860. #endif
  861. addic. I, I, -1
  862. bgt LL(11)
  863. .align 4
  864. LL(20):
  865. andi. I, M, 1
  866. ble LL(29)
  867. #if defined(LT) || defined(RN)
  868. LFD f16, 0 * SIZE(AO)
  869. LFD f17, 1 * SIZE(AO)
  870. LFD f18, 2 * SIZE(AO)
  871. LFD f19, 3 * SIZE(AO)
  872. LFD f20, 0 * SIZE(B)
  873. LFD f21, 1 * SIZE(B)
  874. LFD f22, 2 * SIZE(B)
  875. LFD f23, 3 * SIZE(B)
  876. LFD f24, 4 * SIZE(B)
  877. LFD f25, 5 * SIZE(B)
  878. LFD f26, 6 * SIZE(B)
  879. LFD f27, 7 * SIZE(B)
  880. lfs f0, FZERO
  881. fmr f1, f0
  882. fmr f2, f0
  883. fmr f3, f0
  884. fmr f4, f0
  885. fmr f5, f0
  886. fmr f6, f0
  887. fmr f7, f0
  888. srawi. r0, KK, 2
  889. mr BO, B
  890. mtspr CTR, r0
  891. #else
  892. #ifdef LN
  893. slwi r0, K, 0 + ZBASE_SHIFT
  894. sub AORIG, AORIG, r0
  895. #endif
  896. slwi r0, KK, 0 + ZBASE_SHIFT
  897. slwi TEMP, KK, 1 + ZBASE_SHIFT
  898. add AO, AORIG, r0
  899. add BO, B, TEMP
  900. sub TEMP, K, KK
  901. LFD f16, 0 * SIZE(AO)
  902. LFD f17, 1 * SIZE(AO)
  903. LFD f18, 2 * SIZE(AO)
  904. LFD f19, 3 * SIZE(AO)
  905. LFD f20, 0 * SIZE(BO)
  906. LFD f21, 1 * SIZE(BO)
  907. LFD f22, 2 * SIZE(BO)
  908. LFD f23, 3 * SIZE(BO)
  909. LFD f24, 4 * SIZE(BO)
  910. LFD f25, 5 * SIZE(BO)
  911. LFD f26, 6 * SIZE(BO)
  912. LFD f27, 7 * SIZE(BO)
  913. lfs f0, FZERO
  914. fmr f1, f0
  915. fmr f2, f0
  916. fmr f3, f0
  917. fmr f4, f0
  918. fmr f5, f0
  919. fmr f6, f0
  920. fmr f7, f0
  921. srawi. r0, TEMP, 2
  922. mtspr CTR, r0
  923. #endif
  924. ble LL(25)
  925. .align 4
  926. LL(22):
  927. fmadd f0, f16, f20, f0
  928. fmadd f1, f16, f21, f1
  929. fmadd f2, f16, f22, f2
  930. fmadd f3, f16, f23, f3
  931. fmadd f4, f17, f20, f4
  932. fmadd f5, f17, f21, f5
  933. fmadd f6, f17, f22, f6
  934. fmadd f7, f17, f23, f7
  935. LFD f20, 8 * SIZE(BO)
  936. LFD f21, 9 * SIZE(BO)
  937. LFD f22, 10 * SIZE(BO)
  938. LFD f23, 11 * SIZE(BO)
  939. fmadd f0, f18, f24, f0
  940. fmadd f1, f18, f25, f1
  941. fmadd f2, f18, f26, f2
  942. fmadd f3, f18, f27, f3
  943. fmadd f4, f19, f24, f4
  944. fmadd f5, f19, f25, f5
  945. fmadd f6, f19, f26, f6
  946. fmadd f7, f19, f27, f7
  947. LFD f24, 12 * SIZE(BO)
  948. LFD f25, 13 * SIZE(BO)
  949. LFD f26, 14 * SIZE(BO)
  950. LFD f27, 15 * SIZE(BO)
  951. LFD f16, 4 * SIZE(AO)
  952. LFD f17, 5 * SIZE(AO)
  953. LFD f18, 6 * SIZE(AO)
  954. LFD f19, 7 * SIZE(AO)
  955. fmadd f0, f16, f20, f0
  956. fmadd f1, f16, f21, f1
  957. fmadd f2, f16, f22, f2
  958. fmadd f3, f16, f23, f3
  959. fmadd f4, f17, f20, f4
  960. fmadd f5, f17, f21, f5
  961. fmadd f6, f17, f22, f6
  962. fmadd f7, f17, f23, f7
  963. LFD f20, 16 * SIZE(BO)
  964. LFD f21, 17 * SIZE(BO)
  965. LFD f22, 18 * SIZE(BO)
  966. LFD f23, 19 * SIZE(BO)
  967. fmadd f0, f18, f24, f0
  968. fmadd f1, f18, f25, f1
  969. fmadd f2, f18, f26, f2
  970. fmadd f3, f18, f27, f3
  971. fmadd f4, f19, f24, f4
  972. fmadd f5, f19, f25, f5
  973. fmadd f6, f19, f26, f6
  974. fmadd f7, f19, f27, f7
  975. LFD f16, 8 * SIZE(AO)
  976. LFD f17, 9 * SIZE(AO)
  977. LFD f18, 10 * SIZE(AO)
  978. LFD f19, 11 * SIZE(AO)
  979. LFD f24, 20 * SIZE(BO)
  980. LFD f25, 21 * SIZE(BO)
  981. LFD f26, 22 * SIZE(BO)
  982. LFD f27, 23 * SIZE(BO)
  983. addi BO, BO, 16 * SIZE
  984. addi AO, AO, 8 * SIZE
  985. bdnz LL(22)
  986. .align 4
  987. LL(25):
  988. #if defined(LT) || defined(RN)
  989. andi. r0, KK, 3
  990. #else
  991. andi. r0, TEMP, 3
  992. #endif
  993. mtspr CTR, r0
  994. ble LL(27)
  995. .align 4
  996. LL(26):
  997. fmadd f0, f16, f20, f0
  998. fmadd f1, f16, f21, f1
  999. fmadd f2, f16, f22, f2
  1000. fmadd f3, f16, f23, f3
  1001. fmadd f4, f17, f20, f4
  1002. fmadd f5, f17, f21, f5
  1003. fmadd f6, f17, f22, f6
  1004. fmadd f7, f17, f23, f7
  1005. LFD f20, 4 * SIZE(BO)
  1006. LFD f21, 5 * SIZE(BO)
  1007. LFD f22, 6 * SIZE(BO)
  1008. LFD f23, 7 * SIZE(BO)
  1009. LFD f16, 2 * SIZE(AO)
  1010. LFD f17, 3 * SIZE(AO)
  1011. addi AO, AO, 2 * SIZE
  1012. addi BO, BO, 4 * SIZE
  1013. bdnz LL(26)
  1014. .align 4
  1015. LL(27):
  1016. #ifndef CONJ
  1017. FSUB f0, f0, f5
  1018. FADD f1, f1, f4
  1019. FSUB f2, f2, f7
  1020. FADD f3, f3, f6
  1021. #else
  1022. #if defined(LN) || defined(LT)
  1023. FADD f0, f0, f5
  1024. FSUB f1, f1, f4
  1025. FADD f2, f2, f7
  1026. FSUB f3, f3, f6
  1027. #else
  1028. FADD f0, f0, f5
  1029. FSUB f1, f4, f1
  1030. FADD f2, f2, f7
  1031. FSUB f3, f6, f3
  1032. #endif
  1033. #endif
  1034. #if defined(LN) || defined(RT)
  1035. #ifdef LN
  1036. subi r0, KK, 1
  1037. #else
  1038. subi r0, KK, 2
  1039. #endif
  1040. slwi TEMP, r0, 0 + ZBASE_SHIFT
  1041. slwi r0, r0, 1 + ZBASE_SHIFT
  1042. add AO, AORIG, TEMP
  1043. add BO, B, r0
  1044. #endif
  1045. #if defined(LN) || defined(LT)
  1046. LFD f16, 0 * SIZE(BO)
  1047. LFD f17, 1 * SIZE(BO)
  1048. LFD f18, 2 * SIZE(BO)
  1049. LFD f19, 3 * SIZE(BO)
  1050. FSUB f0, f16, f0
  1051. FSUB f1, f17, f1
  1052. FSUB f2, f18, f2
  1053. FSUB f3, f19, f3
  1054. #else
  1055. LFD f16, 0 * SIZE(AO)
  1056. LFD f17, 1 * SIZE(AO)
  1057. LFD f20, 2 * SIZE(AO)
  1058. LFD f21, 3 * SIZE(AO)
  1059. FSUB f0, f16, f0
  1060. FSUB f1, f17, f1
  1061. FSUB f2, f20, f2
  1062. FSUB f3, f21, f3
  1063. #endif
  1064. #ifdef LN
  1065. LFD f20, 0 * SIZE(AO)
  1066. LFD f21, 1 * SIZE(AO)
  1067. FMUL f4, f21, f1
  1068. FMUL f5, f21, f0
  1069. FMUL f12, f21, f3
  1070. FMUL f13, f21, f2
  1071. #ifndef CONJ
  1072. FMSUB f0, f20, f0, f4
  1073. FMADD f1, f20, f1, f5
  1074. FMSUB f2, f20, f2, f12
  1075. FMADD f3, f20, f3, f13
  1076. #else
  1077. FMADD f0, f20, f0, f4
  1078. FMSUB f1, f20, f1, f5
  1079. FMADD f2, f20, f2, f12
  1080. FMSUB f3, f20, f3, f13
  1081. #endif
  1082. #endif
  1083. #ifdef LT
  1084. LFD f16, 0 * SIZE(AO)
  1085. LFD f17, 1 * SIZE(AO)
  1086. FMUL f4, f17, f1
  1087. FMUL f5, f17, f0
  1088. FMUL f12, f17, f3
  1089. FMUL f13, f17, f2
  1090. #ifndef CONJ
  1091. FMSUB f0, f16, f0, f4
  1092. FMADD f1, f16, f1, f5
  1093. FMSUB f2, f16, f2, f12
  1094. FMADD f3, f16, f3, f13
  1095. #else
  1096. FMADD f0, f16, f0, f4
  1097. FMSUB f1, f16, f1, f5
  1098. FMADD f2, f16, f2, f12
  1099. FMSUB f3, f16, f3, f13
  1100. #endif
  1101. #endif
  1102. #ifdef RN
  1103. LFD f16, 0 * SIZE(BO)
  1104. LFD f17, 1 * SIZE(BO)
  1105. LFD f18, 2 * SIZE(BO)
  1106. LFD f19, 3 * SIZE(BO)
  1107. LFD f20, 6 * SIZE(BO)
  1108. LFD f21, 7 * SIZE(BO)
  1109. FMUL f4, f17, f1
  1110. FMUL f5, f17, f0
  1111. #ifndef CONJ
  1112. FMSUB f0, f16, f0, f4
  1113. FMADD f1, f16, f1, f5
  1114. FMADD f2, f19, f1, f2
  1115. FNMSUB f3, f19, f0, f3
  1116. FNMSUB f2, f18, f0, f2
  1117. FNMSUB f3, f18, f1, f3
  1118. FMUL f4, f21, f3
  1119. FMUL f5, f21, f2
  1120. FMSUB f2, f20, f2, f4
  1121. FMADD f3, f20, f3, f5
  1122. #else
  1123. FMADD f0, f16, f0, f4
  1124. FMSUB f1, f16, f1, f5
  1125. FMSUB f2, f19, f1, f2
  1126. FNMADD f3, f19, f0, f3
  1127. FNMADD f2, f18, f0, f2
  1128. FNMADD f3, f18, f1, f3
  1129. FMUL f4, f21, f3
  1130. FMUL f5, f21, f2
  1131. FMADD f2, f20, f2, f4
  1132. FMSUB f3, f20, f3, f5
  1133. #endif
  1134. #endif
  1135. #ifdef RT
  1136. LFD f16, 6 * SIZE(BO)
  1137. LFD f17, 7 * SIZE(BO)
  1138. LFD f18, 4 * SIZE(BO)
  1139. LFD f19, 5 * SIZE(BO)
  1140. LFD f20, 0 * SIZE(BO)
  1141. LFD f21, 1 * SIZE(BO)
  1142. FMUL f12, f17, f3
  1143. FMUL f13, f17, f2
  1144. #ifndef CONJ
  1145. FMSUB f2, f16, f2, f12
  1146. FMADD f3, f16, f3, f13
  1147. FMADD f0, f19, f3, f0
  1148. FNMSUB f1, f19, f2, f1
  1149. FNMSUB f0, f18, f2, f0
  1150. FNMSUB f1, f18, f3, f1
  1151. FMUL f4, f21, f1
  1152. FMUL f5, f21, f0
  1153. FMSUB f0, f20, f0, f4
  1154. FMADD f1, f20, f1, f5
  1155. #else
  1156. FMADD f2, f16, f2, f12
  1157. FMSUB f3, f16, f3, f13
  1158. FMSUB f0, f19, f3, f0
  1159. FNMADD f1, f19, f2, f1
  1160. FNMADD f0, f18, f2, f0
  1161. FNMADD f1, f18, f3, f1
  1162. FMUL f4, f21, f1
  1163. FMUL f5, f21, f0
  1164. FMADD f0, f20, f0, f4
  1165. FMSUB f1, f20, f1, f5
  1166. #endif
  1167. #endif
  1168. #ifdef LN
  1169. subi CO1, CO1, 2 * SIZE
  1170. subi CO2, CO2, 2 * SIZE
  1171. #endif
  1172. #if defined(LN) || defined(LT)
  1173. STFD f0, 0 * SIZE(BO)
  1174. STFD f1, 1 * SIZE(BO)
  1175. STFD f2, 2 * SIZE(BO)
  1176. STFD f3, 3 * SIZE(BO)
  1177. #else
  1178. STFD f0, 0 * SIZE(AO)
  1179. STFD f1, 1 * SIZE(AO)
  1180. STFD f2, 2 * SIZE(AO)
  1181. STFD f3, 3 * SIZE(AO)
  1182. #endif
  1183. STFD f0, 0 * SIZE(CO1)
  1184. STFD f1, 1 * SIZE(CO1)
  1185. STFD f2, 0 * SIZE(CO2)
  1186. STFD f3, 1 * SIZE(CO2)
  1187. #ifndef LN
  1188. addi CO1, CO1, 2 * SIZE
  1189. addi CO2, CO2, 2 * SIZE
  1190. #endif
  1191. #ifdef RT
  1192. slwi r0, K, 0 + ZBASE_SHIFT
  1193. add AORIG, AORIG, r0
  1194. #endif
  1195. #if defined(LT) || defined(RN)
  1196. sub TEMP, K, KK
  1197. slwi r0, TEMP, 0 + ZBASE_SHIFT
  1198. slwi TEMP, TEMP, 1 + ZBASE_SHIFT
  1199. add AO, AO, r0
  1200. add BO, BO, TEMP
  1201. #endif
  1202. #ifdef LT
  1203. addi KK, KK, 1
  1204. #endif
  1205. #ifdef LN
  1206. subi KK, KK, 1
  1207. #endif
  1208. .align 4
  1209. LL(29):
  1210. #ifdef LN
  1211. slwi r0, K, 1 + ZBASE_SHIFT
  1212. add B, B, r0
  1213. #endif
  1214. #if defined(LT) || defined(RN)
  1215. mr B, BO
  1216. #endif
  1217. #ifdef RN
  1218. addi KK, KK, 2
  1219. #endif
  1220. #ifdef RT
  1221. subi KK, KK, 2
  1222. #endif
  1223. addic. J, J, -1
  1224. bgt LL(10)
  1225. .align 4
  1226. LL(30):
  1227. andi. J, N, 1
  1228. ble LL(999)
  1229. #ifdef RT
  1230. slwi r0, K, 0 + ZBASE_SHIFT
  1231. sub B, B, r0
  1232. sub C, C, LDC
  1233. #endif
  1234. mr CO1, C
  1235. #ifdef LN
  1236. add KK, M, OFFSET
  1237. #endif
  1238. #ifdef LT
  1239. mr KK, OFFSET
  1240. #endif
  1241. srawi. I, M, 1
  1242. #if defined(LN) || defined(RT)
  1243. mr AORIG, A
  1244. #else
  1245. mr AO, A
  1246. #endif
  1247. #ifndef RT
  1248. add C, C, LDC
  1249. #endif
  1250. ble LL(40)
  1251. .align 4
  1252. LL(31):
  1253. #if defined(LT) || defined(RN)
  1254. LFD f20, 0 * SIZE(AO)
  1255. LFD f21, 1 * SIZE(AO)
  1256. LFD f22, 2 * SIZE(AO)
  1257. LFD f23, 3 * SIZE(AO)
  1258. LFD f24, 4 * SIZE(AO)
  1259. LFD f25, 5 * SIZE(AO)
  1260. LFD f26, 6 * SIZE(AO)
  1261. LFD f27, 7 * SIZE(AO)
  1262. LFD f16, 0 * SIZE(B)
  1263. LFD f17, 1 * SIZE(B)
  1264. LFD f18, 2 * SIZE(B)
  1265. LFD f19, 3 * SIZE(B)
  1266. lfs f0, FZERO
  1267. fmr f1, f0
  1268. fmr f2, f0
  1269. fmr f3, f0
  1270. fmr f4, f0
  1271. fmr f5, f0
  1272. fmr f6, f0
  1273. fmr f7, f0
  1274. dcbt CO1, PREC
  1275. srawi. r0, KK, 2
  1276. mr BO, B
  1277. mtspr CTR, r0
  1278. #else
  1279. #ifdef LN
  1280. slwi r0, K, 1 + ZBASE_SHIFT
  1281. sub AORIG, AORIG, r0
  1282. #endif
  1283. slwi r0, KK, 1 + ZBASE_SHIFT
  1284. slwi TEMP, KK, 0 + ZBASE_SHIFT
  1285. add AO, AORIG, r0
  1286. add BO, B, TEMP
  1287. sub TEMP, K, KK
  1288. LFD f20, 0 * SIZE(AO)
  1289. LFD f21, 1 * SIZE(AO)
  1290. LFD f22, 2 * SIZE(AO)
  1291. LFD f23, 3 * SIZE(AO)
  1292. LFD f24, 4 * SIZE(AO)
  1293. LFD f25, 5 * SIZE(AO)
  1294. LFD f26, 6 * SIZE(AO)
  1295. LFD f27, 7 * SIZE(AO)
  1296. LFD f16, 0 * SIZE(BO)
  1297. LFD f17, 1 * SIZE(BO)
  1298. LFD f18, 2 * SIZE(BO)
  1299. LFD f19, 3 * SIZE(BO)
  1300. lfs f0, FZERO
  1301. fmr f1, f0
  1302. fmr f2, f0
  1303. fmr f3, f0
  1304. fmr f4, f0
  1305. fmr f5, f0
  1306. fmr f6, f0
  1307. fmr f7, f0
  1308. srawi. r0, TEMP, 2
  1309. mtspr CTR, r0
  1310. #endif
  1311. ble LL(35)
  1312. .align 4
  1313. LL(32):
  1314. fmadd f0, f16, f20, f0
  1315. fmadd f1, f16, f21, f1
  1316. fmadd f2, f16, f22, f2
  1317. fmadd f3, f16, f23, f3
  1318. fmadd f4, f17, f20, f4
  1319. fmadd f5, f17, f21, f5
  1320. fmadd f6, f17, f22, f6
  1321. fmadd f7, f17, f23, f7
  1322. LFD f20, 8 * SIZE(AO)
  1323. LFD f21, 9 * SIZE(AO)
  1324. LFD f22, 10 * SIZE(AO)
  1325. LFD f23, 11 * SIZE(AO)
  1326. fmadd f0, f18, f24, f0
  1327. fmadd f1, f18, f25, f1
  1328. fmadd f2, f18, f26, f2
  1329. fmadd f3, f18, f27, f3
  1330. fmadd f4, f19, f24, f4
  1331. fmadd f5, f19, f25, f5
  1332. fmadd f6, f19, f26, f6
  1333. fmadd f7, f19, f27, f7
  1334. LFD f24, 12 * SIZE(AO)
  1335. LFD f25, 13 * SIZE(AO)
  1336. LFD f26, 14 * SIZE(AO)
  1337. LFD f27, 15 * SIZE(AO)
  1338. LFD f16, 4 * SIZE(BO)
  1339. LFD f17, 5 * SIZE(BO)
  1340. LFD f18, 6 * SIZE(BO)
  1341. LFD f19, 7 * SIZE(BO)
  1342. fmadd f0, f16, f20, f0
  1343. fmadd f1, f16, f21, f1
  1344. fmadd f2, f16, f22, f2
  1345. fmadd f3, f16, f23, f3
  1346. fmadd f4, f17, f20, f4
  1347. fmadd f5, f17, f21, f5
  1348. fmadd f6, f17, f22, f6
  1349. fmadd f7, f17, f23, f7
  1350. LFD f20, 16 * SIZE(AO)
  1351. LFD f21, 17 * SIZE(AO)
  1352. LFD f22, 18 * SIZE(AO)
  1353. LFD f23, 19 * SIZE(AO)
  1354. fmadd f0, f18, f24, f0
  1355. fmadd f1, f18, f25, f1
  1356. fmadd f2, f18, f26, f2
  1357. fmadd f3, f18, f27, f3
  1358. fmadd f4, f19, f24, f4
  1359. fmadd f5, f19, f25, f5
  1360. fmadd f6, f19, f26, f6
  1361. fmadd f7, f19, f27, f7
  1362. LFD f24, 20 * SIZE(AO)
  1363. LFD f25, 21 * SIZE(AO)
  1364. LFD f26, 22 * SIZE(AO)
  1365. LFD f27, 23 * SIZE(AO)
  1366. LFD f16, 8 * SIZE(BO)
  1367. LFD f17, 9 * SIZE(BO)
  1368. LFD f18, 10 * SIZE(BO)
  1369. LFD f19, 11 * SIZE(BO)
  1370. addi AO, AO, 16 * SIZE
  1371. addi BO, BO, 8 * SIZE
  1372. dcbt PREA, AO
  1373. dcbt PREA, BO
  1374. bdnz LL(32)
  1375. .align 4
  1376. LL(35):
  1377. #if defined(LT) || defined(RN)
  1378. andi. r0, KK, 3
  1379. #else
  1380. andi. r0, TEMP, 3
  1381. #endif
  1382. mtspr CTR, r0
  1383. ble LL(37)
  1384. .align 4
  1385. LL(36):
  1386. fmadd f0, f16, f20, f0
  1387. fmadd f1, f16, f21, f1
  1388. fmadd f2, f16, f22, f2
  1389. fmadd f3, f16, f23, f3
  1390. fmadd f4, f17, f20, f4
  1391. fmadd f5, f17, f21, f5
  1392. fmadd f6, f17, f22, f6
  1393. fmadd f7, f17, f23, f7
  1394. LFD f20, 4 * SIZE(AO)
  1395. LFD f21, 5 * SIZE(AO)
  1396. LFD f22, 6 * SIZE(AO)
  1397. LFD f23, 7 * SIZE(AO)
  1398. LFD f16, 2 * SIZE(BO)
  1399. LFD f17, 3 * SIZE(BO)
  1400. addi BO, BO, 2 * SIZE
  1401. addi AO, AO, 4 * SIZE
  1402. bdnz LL(36)
  1403. .align 4
  1404. LL(37):
  1405. #ifndef CONJ
  1406. FSUB f0, f0, f5
  1407. FADD f1, f1, f4
  1408. FSUB f2, f2, f7
  1409. FADD f3, f3, f6
  1410. #else
  1411. FADD f0, f0, f5
  1412. FSUB f1, f4, f1
  1413. FADD f2, f2, f7
  1414. FSUB f3, f6, f3
  1415. #endif
  1416. #if defined(LN) || defined(RT)
  1417. #ifdef LN
  1418. subi r0, KK, 2
  1419. #else
  1420. subi r0, KK, 1
  1421. #endif
  1422. slwi TEMP, r0, 1 + ZBASE_SHIFT
  1423. slwi r0, r0, 0 + ZBASE_SHIFT
  1424. add AO, AORIG, TEMP
  1425. add BO, B, r0
  1426. #endif
  1427. #if defined(LN) || defined(LT)
  1428. LFD f16, 0 * SIZE(BO)
  1429. LFD f17, 1 * SIZE(BO)
  1430. LFD f18, 2 * SIZE(BO)
  1431. LFD f19, 3 * SIZE(BO)
  1432. FSUB f0, f16, f0
  1433. FSUB f1, f17, f1
  1434. FSUB f2, f18, f2
  1435. FSUB f3, f19, f3
  1436. #else
  1437. LFD f16, 0 * SIZE(AO)
  1438. LFD f17, 1 * SIZE(AO)
  1439. LFD f18, 2 * SIZE(AO)
  1440. LFD f19, 3 * SIZE(AO)
  1441. #ifndef CONJ
  1442. FSUB f0, f16, f0
  1443. FSUB f1, f17, f1
  1444. FSUB f2, f18, f2
  1445. FSUB f3, f19, f3
  1446. #else
  1447. FSUB f0, f16, f0
  1448. FADD f1, f17, f1
  1449. FSUB f2, f18, f2
  1450. FADD f3, f19, f3
  1451. #endif
  1452. #endif
  1453. #ifdef LN
  1454. LFD f16, 6 * SIZE(AO)
  1455. LFD f17, 7 * SIZE(AO)
  1456. LFD f18, 4 * SIZE(AO)
  1457. LFD f19, 5 * SIZE(AO)
  1458. LFD f20, 0 * SIZE(AO)
  1459. LFD f21, 1 * SIZE(AO)
  1460. FMUL f6, f17, f3
  1461. FMUL f7, f17, f2
  1462. #ifndef CONJ
  1463. FMSUB f2, f16, f2, f6
  1464. FMADD f3, f16, f3, f7
  1465. FMADD f0, f19, f3, f0
  1466. FNMSUB f1, f19, f2, f1
  1467. FNMSUB f0, f18, f2, f0
  1468. FNMSUB f1, f18, f3, f1
  1469. FMUL f4, f21, f1
  1470. FMUL f5, f21, f0
  1471. FMSUB f0, f20, f0, f4
  1472. FMADD f1, f20, f1, f5
  1473. #else
  1474. FMADD f2, f16, f2, f6
  1475. FMSUB f3, f16, f3, f7
  1476. FMSUB f0, f19, f3, f0
  1477. FNMADD f1, f19, f2, f1
  1478. FNMADD f0, f18, f2, f0
  1479. FNMADD f1, f18, f3, f1
  1480. FMUL f4, f21, f1
  1481. FMUL f5, f21, f0
  1482. FMADD f0, f20, f0, f4
  1483. FMSUB f1, f20, f1, f5
  1484. #endif
  1485. #endif
  1486. #ifdef LT
  1487. LFD f16, 0 * SIZE(AO)
  1488. LFD f17, 1 * SIZE(AO)
  1489. LFD f18, 2 * SIZE(AO)
  1490. LFD f19, 3 * SIZE(AO)
  1491. LFD f20, 6 * SIZE(AO)
  1492. LFD f21, 7 * SIZE(AO)
  1493. FMUL f4, f17, f1
  1494. FMUL f5, f17, f0
  1495. #ifndef CONJ
  1496. FMSUB f0, f16, f0, f4
  1497. FMADD f1, f16, f1, f5
  1498. FMADD f2, f19, f1, f2
  1499. FNMSUB f3, f19, f0, f3
  1500. FNMSUB f2, f18, f0, f2
  1501. FNMSUB f3, f18, f1, f3
  1502. FMUL f4, f21, f3
  1503. FMUL f5, f21, f2
  1504. FMSUB f2, f20, f2, f4
  1505. FMADD f3, f20, f3, f5
  1506. #else
  1507. FMADD f0, f16, f0, f4
  1508. FMSUB f1, f16, f1, f5
  1509. FMSUB f2, f19, f1, f2
  1510. FNMADD f3, f19, f0, f3
  1511. FNMADD f2, f18, f0, f2
  1512. FNMADD f3, f18, f1, f3
  1513. FMUL f4, f21, f3
  1514. FMUL f5, f21, f2
  1515. FMADD f2, f20, f2, f4
  1516. FMSUB f3, f20, f3, f5
  1517. #endif
  1518. #endif
  1519. #ifdef RN
  1520. LFD f16, 0 * SIZE(BO)
  1521. LFD f17, 1 * SIZE(BO)
  1522. FMUL f4, f17, f1
  1523. FMUL f5, f17, f0
  1524. FMUL f6, f17, f3
  1525. FMUL f7, f17, f2
  1526. #ifndef CONJ
  1527. FMSUB f0, f16, f0, f4
  1528. FMADD f1, f16, f1, f5
  1529. FMSUB f2, f16, f2, f6
  1530. FMADD f3, f16, f3, f7
  1531. #else
  1532. FMADD f0, f16, f0, f4
  1533. FMSUB f1, f16, f1, f5
  1534. FMADD f2, f16, f2, f6
  1535. FMSUB f3, f16, f3, f7
  1536. #endif
  1537. #endif
  1538. #ifdef RT
  1539. LFD f20, 0 * SIZE(BO)
  1540. LFD f21, 1 * SIZE(BO)
  1541. FMUL f4, f21, f1
  1542. FMUL f5, f21, f0
  1543. FMUL f6, f21, f3
  1544. FMUL f7, f21, f2
  1545. #ifndef CONJ
  1546. FMSUB f0, f20, f0, f4
  1547. FMADD f1, f20, f1, f5
  1548. FMSUB f2, f20, f2, f6
  1549. FMADD f3, f20, f3, f7
  1550. #else
  1551. FMADD f0, f20, f0, f4
  1552. FMSUB f1, f20, f1, f5
  1553. FMADD f2, f20, f2, f6
  1554. FMSUB f3, f20, f3, f7
  1555. #endif
  1556. #endif
  1557. #ifdef LN
  1558. subi CO1, CO1, 4 * SIZE
  1559. #endif
  1560. #if defined(LN) || defined(LT)
  1561. STFD f0, 0 * SIZE(BO)
  1562. STFD f1, 1 * SIZE(BO)
  1563. STFD f2, 2 * SIZE(BO)
  1564. STFD f3, 3 * SIZE(BO)
  1565. #else
  1566. STFD f0, 0 * SIZE(AO)
  1567. STFD f1, 1 * SIZE(AO)
  1568. STFD f2, 2 * SIZE(AO)
  1569. STFD f3, 3 * SIZE(AO)
  1570. #endif
  1571. STFD f0, 0 * SIZE(CO1)
  1572. STFD f1, 1 * SIZE(CO1)
  1573. STFD f2, 2 * SIZE(CO1)
  1574. STFD f3, 3 * SIZE(CO1)
  1575. #ifndef LN
  1576. addi CO1, CO1, 4 * SIZE
  1577. #endif
  1578. #ifdef RT
  1579. slwi r0, K, 1 + ZBASE_SHIFT
  1580. add AORIG, AORIG, r0
  1581. #endif
  1582. #if defined(LT) || defined(RN)
  1583. sub TEMP, K, KK
  1584. slwi r0, TEMP, 1 + ZBASE_SHIFT
  1585. slwi TEMP, TEMP, 0 + ZBASE_SHIFT
  1586. add AO, AO, r0
  1587. add BO, BO, TEMP
  1588. #endif
  1589. #ifdef LT
  1590. addi KK, KK, 2
  1591. #endif
  1592. #ifdef LN
  1593. subi KK, KK, 2
  1594. #endif
  1595. addic. I, I, -1
  1596. bgt LL(31)
  1597. .align 4
  1598. LL(40):
  1599. andi. I, M, 1
  1600. ble LL(49)
  1601. #if defined(LT) || defined(RN)
  1602. LFD f16, 0 * SIZE(AO)
  1603. LFD f17, 1 * SIZE(AO)
  1604. LFD f18, 2 * SIZE(AO)
  1605. LFD f19, 3 * SIZE(AO)
  1606. LFD f20, 0 * SIZE(B)
  1607. LFD f21, 1 * SIZE(B)
  1608. LFD f22, 2 * SIZE(B)
  1609. LFD f23, 3 * SIZE(B)
  1610. lfs f0, FZERO
  1611. fmr f1, f0
  1612. fmr f2, f0
  1613. fmr f3, f0
  1614. fmr f4, f0
  1615. fmr f5, f0
  1616. fmr f6, f0
  1617. fmr f7, f0
  1618. srawi. r0, KK, 2
  1619. mr BO, B
  1620. mtspr CTR, r0
  1621. #else
  1622. #ifdef LN
  1623. slwi r0, K, 0 + ZBASE_SHIFT
  1624. sub AORIG, AORIG, r0
  1625. #endif
  1626. slwi r0, KK, 0 + ZBASE_SHIFT
  1627. add AO, AORIG, r0
  1628. add BO, B, r0
  1629. sub TEMP, K, KK
  1630. LFD f16, 0 * SIZE(AO)
  1631. LFD f17, 1 * SIZE(AO)
  1632. LFD f18, 2 * SIZE(AO)
  1633. LFD f19, 3 * SIZE(AO)
  1634. LFD f20, 0 * SIZE(BO)
  1635. LFD f21, 1 * SIZE(BO)
  1636. LFD f22, 2 * SIZE(BO)
  1637. LFD f23, 3 * SIZE(BO)
  1638. lfs f0, FZERO
  1639. fmr f1, f0
  1640. fmr f2, f0
  1641. fmr f3, f0
  1642. fmr f4, f0
  1643. fmr f5, f0
  1644. fmr f6, f0
  1645. fmr f7, f0
  1646. srawi. r0, TEMP, 2
  1647. mtspr CTR, r0
  1648. #endif
  1649. ble LL(45)
  1650. .align 4
  1651. LL(42):
  1652. fmadd f0, f16, f20, f0
  1653. fmadd f1, f17, f21, f1
  1654. fmadd f2, f17, f20, f2
  1655. fmadd f3, f16, f21, f3
  1656. LFD f16, 4 * SIZE(AO)
  1657. LFD f17, 5 * SIZE(AO)
  1658. LFD f20, 4 * SIZE(BO)
  1659. LFD f21, 5 * SIZE(BO)
  1660. fmadd f4, f18, f22, f4
  1661. fmadd f5, f19, f23, f5
  1662. fmadd f6, f19, f22, f6
  1663. fmadd f7, f18, f23, f7
  1664. LFD f18, 6 * SIZE(AO)
  1665. LFD f19, 7 * SIZE(AO)
  1666. LFD f22, 6 * SIZE(BO)
  1667. LFD f23, 7 * SIZE(BO)
  1668. fmadd f0, f16, f20, f0
  1669. fmadd f1, f17, f21, f1
  1670. fmadd f2, f17, f20, f2
  1671. fmadd f3, f16, f21, f3
  1672. LFD f16, 8 * SIZE(AO)
  1673. LFD f17, 9 * SIZE(AO)
  1674. LFD f20, 8 * SIZE(BO)
  1675. LFD f21, 9 * SIZE(BO)
  1676. fmadd f4, f18, f22, f4
  1677. fmadd f5, f19, f23, f5
  1678. fmadd f6, f19, f22, f6
  1679. fmadd f7, f18, f23, f7
  1680. LFD f18, 10 * SIZE(AO)
  1681. LFD f19, 11 * SIZE(AO)
  1682. LFD f22, 10 * SIZE(BO)
  1683. LFD f23, 11 * SIZE(BO)
  1684. addi AO, AO, 8 * SIZE
  1685. addi BO, BO, 8 * SIZE
  1686. bdnz LL(42)
  1687. .align 4
  1688. LL(45):
  1689. fadd f0, f0, f4
  1690. fadd f1, f1, f5
  1691. fadd f2, f2, f6
  1692. fadd f3, f3, f7
  1693. #if defined(LT) || defined(RN)
  1694. andi. r0, KK, 3
  1695. #else
  1696. andi. r0, TEMP, 3
  1697. #endif
  1698. mtspr CTR,r0
  1699. ble LL(47)
  1700. .align 4
  1701. LL(46):
  1702. fmadd f0, f16, f20, f0
  1703. fmadd f1, f17, f21, f1
  1704. fmadd f2, f17, f20, f2
  1705. fmadd f3, f16, f21, f3
  1706. LFD f16, 2 * SIZE(AO)
  1707. LFD f17, 3 * SIZE(AO)
  1708. LFD f20, 2 * SIZE(BO)
  1709. LFD f21, 3 * SIZE(BO)
  1710. addi AO, AO, 2 * SIZE
  1711. addi BO, BO, 2 * SIZE
  1712. bdnz LL(46)
  1713. .align 4
  1714. LL(47):
  1715. #ifndef CONJ
  1716. FSUB f0, f0, f1
  1717. FADD f1, f2, f3
  1718. #else
  1719. FADD f0, f0, f1
  1720. FSUB f1, f3, f2
  1721. #endif
  1722. #if defined(LN) || defined(RT)
  1723. subi r0, KK, 1
  1724. slwi r0, r0, 0 + ZBASE_SHIFT
  1725. add AO, AORIG, r0
  1726. add BO, B, r0
  1727. #endif
  1728. #if defined(LN) || defined(LT)
  1729. LFD f16, 0 * SIZE(BO)
  1730. LFD f17, 1 * SIZE(BO)
  1731. FSUB f0, f16, f0
  1732. FSUB f1, f17, f1
  1733. #else
  1734. LFD f16, 0 * SIZE(AO)
  1735. LFD f17, 1 * SIZE(AO)
  1736. #ifndef CONJ
  1737. FSUB f0, f16, f0
  1738. FSUB f1, f17, f1
  1739. #else
  1740. FSUB f0, f16, f0
  1741. FADD f1, f17, f1
  1742. #endif
  1743. #endif
  1744. #ifdef LN
  1745. LFD f20, 0 * SIZE(AO)
  1746. LFD f21, 1 * SIZE(AO)
  1747. FMUL f4, f21, f1
  1748. FMUL f5, f21, f0
  1749. #ifndef CONJ
  1750. FMSUB f0, f20, f0, f4
  1751. FMADD f1, f20, f1, f5
  1752. #else
  1753. FMADD f0, f20, f0, f4
  1754. FMSUB f1, f20, f1, f5
  1755. #endif
  1756. #endif
  1757. #ifdef LT
  1758. LFD f16, 0 * SIZE(AO)
  1759. LFD f17, 1 * SIZE(AO)
  1760. FMUL f4, f17, f1
  1761. FMUL f5, f17, f0
  1762. #ifndef CONJ
  1763. FMSUB f0, f16, f0, f4
  1764. FMADD f1, f16, f1, f5
  1765. #else
  1766. FMADD f0, f16, f0, f4
  1767. FMSUB f1, f16, f1, f5
  1768. #endif
  1769. #endif
  1770. #ifdef RN
  1771. LFD f16, 0 * SIZE(BO)
  1772. LFD f17, 1 * SIZE(BO)
  1773. FMUL f4, f17, f1
  1774. FMUL f5, f17, f0
  1775. #ifndef CONJ
  1776. FMSUB f0, f16, f0, f4
  1777. FMADD f1, f16, f1, f5
  1778. #else
  1779. FMADD f0, f16, f0, f4
  1780. FMSUB f1, f16, f1, f5
  1781. #endif
  1782. #endif
  1783. #ifdef RT
  1784. LFD f20, 0 * SIZE(BO)
  1785. LFD f21, 1 * SIZE(BO)
  1786. FMUL f4, f21, f1
  1787. FMUL f5, f21, f0
  1788. #ifndef CONJ
  1789. FMSUB f0, f20, f0, f4
  1790. FMADD f1, f20, f1, f5
  1791. #else
  1792. FMADD f0, f20, f0, f4
  1793. FMSUB f1, f20, f1, f5
  1794. #endif
  1795. #endif
  1796. #ifdef LN
  1797. subi CO1, CO1, 2 * SIZE
  1798. #endif
  1799. #if defined(LN) || defined(LT)
  1800. STFD f0, 0 * SIZE(BO)
  1801. STFD f1, 1 * SIZE(BO)
  1802. #else
  1803. STFD f0, 0 * SIZE(AO)
  1804. STFD f1, 1 * SIZE(AO)
  1805. #endif
  1806. STFD f0, 0 * SIZE(CO1)
  1807. STFD f1, 1 * SIZE(CO1)
  1808. #ifndef LN
  1809. addi CO1, CO1, 2 * SIZE
  1810. #endif
  1811. #ifdef RT
  1812. slwi r0, K, 0 + ZBASE_SHIFT
  1813. add AORIG, AORIG, r0
  1814. #endif
  1815. #if defined(LT) || defined(RN)
  1816. sub TEMP, K, KK
  1817. slwi TEMP, TEMP, 0 + ZBASE_SHIFT
  1818. add AO, AO, TEMP
  1819. add BO, BO, TEMP
  1820. #endif
  1821. #ifdef LT
  1822. addi KK, KK, 1
  1823. #endif
  1824. #ifdef LN
  1825. subi KK, KK, 1
  1826. #endif
  1827. .align 4
  1828. LL(49):
  1829. #ifdef LN
  1830. slwi r0, K, 0 + ZBASE_SHIFT
  1831. add B, B, r0
  1832. #endif
  1833. #if defined(LT) || defined(RN)
  1834. mr B, BO
  1835. #endif
  1836. #ifdef RN
  1837. addi KK, KK, 1
  1838. #endif
  1839. #ifdef RT
  1840. subi KK, KK, 1
  1841. #endif
  1842. .align 4
  1843. LL(999):
  1844. addi r3, 0, 0
  1845. lfd f14, 0(SP)
  1846. lfd f15, 8(SP)
  1847. lfd f16, 16(SP)
  1848. lfd f17, 24(SP)
  1849. lfd f18, 32(SP)
  1850. lfd f19, 40(SP)
  1851. lfd f20, 48(SP)
  1852. lfd f21, 56(SP)
  1853. lfd f22, 64(SP)
  1854. lfd f23, 72(SP)
  1855. lfd f24, 80(SP)
  1856. lfd f25, 88(SP)
  1857. lfd f26, 96(SP)
  1858. lfd f27, 104(SP)
  1859. lfd f28, 112(SP)
  1860. lfd f29, 120(SP)
  1861. lfd f30, 128(SP)
  1862. lfd f31, 136(SP)
  1863. #ifdef __64BIT__
  1864. ld r31, 144(SP)
  1865. ld r30, 152(SP)
  1866. ld r29, 160(SP)
  1867. ld r28, 168(SP)
  1868. ld r27, 176(SP)
  1869. ld r26, 184(SP)
  1870. ld r25, 192(SP)
  1871. ld r24, 200(SP)
  1872. ld r23, 208(SP)
  1873. ld r22, 216(SP)
  1874. ld r21, 224(SP)
  1875. #else
  1876. lwz r31, 144(SP)
  1877. lwz r30, 148(SP)
  1878. lwz r29, 152(SP)
  1879. lwz r28, 156(SP)
  1880. lwz r27, 160(SP)
  1881. lwz r26, 164(SP)
  1882. lwz r25, 168(SP)
  1883. lwz r24, 172(SP)
  1884. lwz r23, 176(SP)
  1885. lwz r22, 180(SP)
  1886. lwz r21, 184(SP)
  1887. #endif
  1888. addi SP, SP, STACKSIZE
  1889. blr
  1890. EPILOGUE
  1891. #endif