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zgemm_kernel_power6.S 54 kB

rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
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  14. /* copyright notice, this list of conditions and the following */
  15. /* disclaimer in the documentation and/or other materials */
  16. /* provided with the distribution. */
  17. /* */
  18. /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
  19. /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
  20. /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
  21. /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
  22. /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
  23. /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
  24. /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
  25. /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
  26. /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
  27. /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
  28. /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
  29. /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
  30. /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
  31. /* POSSIBILITY OF SUCH DAMAGE. */
  32. /* */
  33. /* The views and conclusions contained in the software and */
  34. /* documentation are those of the authors and should not be */
  35. /* interpreted as representing official policies, either expressed */
  36. /* or implied, of The University of Texas at Austin. */
  37. /*********************************************************************/
  38. #define ASSEMBLER
  39. #include "common.h"
  40. #ifndef __64BIT__
  41. #define LOAD lwz
  42. #else
  43. #define LOAD ld
  44. #endif
  45. #ifdef __64BIT__
  46. #define STACKSIZE 320
  47. #define ALPHA_R 296(SP)
  48. #define ALPHA_I 304(SP)
  49. #define FZERO 312(SP)
  50. #else
  51. #define STACKSIZE 256
  52. #define ALPHA_R 224(SP)
  53. #define ALPHA_I 232(SP)
  54. #define FZERO 240(SP)
  55. #endif
  56. #define M r3
  57. #define N r4
  58. #define K r5
  59. #if defined(linux) || defined(__FreeBSD__)
  60. #ifndef __64BIT__
  61. #define A r6
  62. #define B r7
  63. #define C r8
  64. #define LDC r9
  65. #define OFFSET r10
  66. #else
  67. #define A r8
  68. #define B r9
  69. #define C r10
  70. #define LDC r6
  71. #define OFFSET r7
  72. #endif
  73. #endif
  74. #if defined(_AIX) || defined(__APPLE__)
  75. #if !defined(__64BIT__) && defined(DOUBLE)
  76. #define A r10
  77. #define B r6
  78. #define C r7
  79. #define LDC r8
  80. #define OFFSET r9
  81. #else
  82. #define A r8
  83. #define B r9
  84. #define C r10
  85. #define LDC r6
  86. #define OFFSET r7
  87. #endif
  88. #endif
  89. #define TEMP r19
  90. #define KK r20
  91. #define BB r21
  92. #define I r22
  93. #define J r23
  94. #define AO r24
  95. #define BO r25
  96. #define CO1 r26
  97. #define CO2 r27
  98. #define CO3 r28
  99. #define CO4 r29
  100. #define PREA r30
  101. #define PREC r31
  102. #if defined(NN) || defined(NT) || defined(TN) || defined(TT)
  103. #define FMA1 FMADD
  104. #define FMA2 FMADD
  105. #define FMA3 FNMSUB
  106. #define FMA4 FMADD
  107. #elif defined(NR) || defined(NC) || defined(TR) || defined(TC)
  108. #define FMA1 FMADD
  109. #define FMA2 FNMSUB
  110. #define FMA3 FMADD
  111. #define FMA4 FMADD
  112. #elif defined(RN) || defined(RT) || defined(CN) || defined(CT)
  113. #define FMA1 FMADD
  114. #define FMA2 FMADD
  115. #define FMA3 FMADD
  116. #define FMA4 FNMSUB
  117. #else
  118. #define FMA1 FMADD
  119. #define FMA2 FNMSUB
  120. #define FMA3 FNMSUB
  121. #define FMA4 FNMSUB
  122. #endif
  123. #ifndef NEEDPARAM
  124. PROLOGUE
  125. PROFCODE
  126. addi SP, SP, -STACKSIZE
  127. li r0, 0
  128. stfd f14, 0(SP)
  129. stfd f15, 8(SP)
  130. stfd f16, 16(SP)
  131. stfd f17, 24(SP)
  132. stfd f18, 32(SP)
  133. stfd f19, 40(SP)
  134. stfd f20, 48(SP)
  135. stfd f21, 56(SP)
  136. stfd f22, 64(SP)
  137. stfd f23, 72(SP)
  138. stfd f24, 80(SP)
  139. stfd f25, 88(SP)
  140. stfd f26, 96(SP)
  141. stfd f27, 104(SP)
  142. stfd f28, 112(SP)
  143. stfd f29, 120(SP)
  144. stfd f30, 128(SP)
  145. stfd f31, 136(SP)
  146. #ifdef __64BIT__
  147. std r31, 144(SP)
  148. std r30, 152(SP)
  149. std r29, 160(SP)
  150. std r28, 168(SP)
  151. std r27, 176(SP)
  152. std r26, 184(SP)
  153. std r25, 192(SP)
  154. std r24, 200(SP)
  155. std r23, 208(SP)
  156. std r22, 216(SP)
  157. std r21, 224(SP)
  158. #ifdef TRMMKERNEL
  159. std r20, 232(SP)
  160. std r19, 240(SP)
  161. #endif
  162. #else
  163. stw r31, 144(SP)
  164. stw r30, 148(SP)
  165. stw r29, 152(SP)
  166. stw r28, 156(SP)
  167. stw r27, 160(SP)
  168. stw r26, 164(SP)
  169. stw r25, 168(SP)
  170. stw r24, 172(SP)
  171. stw r23, 176(SP)
  172. stw r22, 180(SP)
  173. stw r21, 184(SP)
  174. #ifdef TRMMKERNEL
  175. stw r20, 188(SP)
  176. stw r19, 192(SP)
  177. #endif
  178. #endif
  179. stfd f1, ALPHA_R
  180. stfd f2, ALPHA_I
  181. stw r0, FZERO
  182. #if defined(linux) || defined(__FreeBSD__)
  183. #ifdef __64BIT__
  184. ld LDC, FRAMESLOT(0) + STACKSIZE(SP)
  185. #endif
  186. #endif
  187. #if defined(_AIX) || defined(__APPLE__)
  188. #ifdef __64BIT__
  189. ld LDC, FRAMESLOT(0) + STACKSIZE(SP)
  190. #else
  191. #ifdef DOUBLE
  192. lwz B, FRAMESLOT(0) + STACKSIZE(SP)
  193. lwz C, FRAMESLOT(1) + STACKSIZE(SP)
  194. lwz LDC, FRAMESLOT(2) + STACKSIZE(SP)
  195. #else
  196. lwz LDC, FRAMESLOT(0) + STACKSIZE(SP)
  197. #endif
  198. #endif
  199. #endif
  200. #ifdef TRMMKERNEL
  201. #if (defined(linux) || defined(__FreeBSD__)) && defined(__64BIT__)
  202. ld OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  203. #endif
  204. #if defined(_AIX) || defined(__APPLE__)
  205. #ifdef __64BIT__
  206. ld OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  207. #else
  208. #ifdef DOUBLE
  209. lwz OFFSET, FRAMESLOT(3) + STACKSIZE(SP)
  210. #else
  211. lwz OFFSET, FRAMESLOT(1) + STACKSIZE(SP)
  212. #endif
  213. #endif
  214. #endif
  215. #if defined(TRMMKERNEL) && !defined(LEFT)
  216. neg KK, OFFSET
  217. #endif
  218. #endif
  219. slwi LDC, LDC, ZBASE_SHIFT
  220. li PREA, (16 * 3) * SIZE
  221. li PREC, 3 * SIZE
  222. cmpwi cr0, M, 0
  223. ble LL(999)
  224. cmpwi cr0, N, 0
  225. ble LL(999)
  226. cmpwi cr0, K, 0
  227. ble LL(999)
  228. srawi. J, N, 2
  229. ble LL(30)
  230. .align 4
  231. LL(10):
  232. mr CO1, C
  233. add CO2, C, LDC
  234. add CO3, CO2, LDC
  235. add CO4, CO3, LDC
  236. add C, CO4, LDC
  237. #if defined(TRMMKERNEL) && defined(LEFT)
  238. mr KK, OFFSET
  239. #endif
  240. slwi BB, K, ZBASE_SHIFT + 2
  241. mr AO, A
  242. lfs f0, FZERO
  243. fmr f1, f0
  244. fmr f2, f0
  245. fmr f3, f0
  246. fmr f4, f0
  247. fmr f5, f0
  248. fmr f6, f0
  249. fmr f7, f0
  250. fmr f8, f0
  251. fmr f9, f0
  252. fmr f10, f0
  253. fmr f11, f0
  254. fmr f12, f0
  255. fmr f13, f0
  256. fmr f14, f0
  257. fmr f15, f0
  258. srawi. I, M, 1
  259. ble LL(20)
  260. .align 4
  261. LL(11):
  262. #ifndef TRMMKERNEL
  263. LFD f16, 0 * SIZE(AO)
  264. LFD f20, 0 * SIZE(B)
  265. LFD f17, 1 * SIZE(AO)
  266. LFD f21, 1 * SIZE(B)
  267. LFD f18, 2 * SIZE(AO)
  268. LFD f22, 2 * SIZE(B)
  269. LFD f19, 3 * SIZE(AO)
  270. LFD f23, 3 * SIZE(B)
  271. LFD f24, 4 * SIZE(B)
  272. LFD f25, 5 * SIZE(B)
  273. LFD f26, 6 * SIZE(B)
  274. LFD f27, 7 * SIZE(B)
  275. dcbtst CO1, PREC
  276. dcbtst CO2, PREC
  277. dcbtst CO3, PREC
  278. dcbtst CO4, PREC
  279. srawi. r0, K, 3
  280. mr BO, B
  281. mtspr CTR, r0
  282. ble LL(15)
  283. #else
  284. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  285. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  286. LFD f16, 0 * SIZE(AO)
  287. LFD f20, 0 * SIZE(B)
  288. LFD f17, 1 * SIZE(AO)
  289. LFD f21, 1 * SIZE(B)
  290. LFD f18, 2 * SIZE(AO)
  291. LFD f22, 2 * SIZE(B)
  292. LFD f19, 3 * SIZE(AO)
  293. LFD f23, 3 * SIZE(B)
  294. LFD f24, 4 * SIZE(B)
  295. LFD f25, 5 * SIZE(B)
  296. LFD f26, 6 * SIZE(B)
  297. LFD f27, 7 * SIZE(B)
  298. mr BO, B
  299. #else
  300. slwi r0, KK, 1 + ZBASE_SHIFT
  301. slwi TEMP, KK, 2 + ZBASE_SHIFT
  302. add AO, AO, r0
  303. add BO, B, TEMP
  304. LFD f16, 0 * SIZE(AO)
  305. LFD f20, 0 * SIZE(BO)
  306. LFD f17, 1 * SIZE(AO)
  307. LFD f21, 1 * SIZE(BO)
  308. LFD f18, 2 * SIZE(AO)
  309. LFD f22, 2 * SIZE(BO)
  310. LFD f19, 3 * SIZE(AO)
  311. LFD f23, 3 * SIZE(BO)
  312. LFD f24, 4 * SIZE(BO)
  313. LFD f25, 5 * SIZE(BO)
  314. LFD f26, 6 * SIZE(BO)
  315. LFD f27, 7 * SIZE(BO)
  316. #endif
  317. dcbtst CO1, PREC
  318. dcbtst CO2, PREC
  319. dcbtst CO3, PREC
  320. dcbtst CO4, PREC
  321. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  322. sub TEMP, K, KK
  323. #elif defined(LEFT)
  324. addi TEMP, KK, 2
  325. #else
  326. addi TEMP, KK, 4
  327. #endif
  328. srawi. TEMP, TEMP, 3
  329. mtspr CTR, TEMP
  330. ble LL(15)
  331. #endif
  332. .align 4
  333. LL(12):
  334. dcbt AO, PREA
  335. FMA1 f0, f16, f20, f0
  336. nop
  337. FMA1 f2, f18, f20, f2
  338. FMA2 f1, f16, f21, f1
  339. FMA2 f3, f18, f21, f3
  340. LFD f28, 4 * SIZE(AO)
  341. LFD f29, 5 * SIZE(AO)
  342. LFD f30, 6 * SIZE(AO)
  343. LFD f31, 7 * SIZE(AO)
  344. FMA1 f4, f16, f22, f4
  345. FMA1 f6, f18, f22, f6
  346. FMA2 f5, f16, f23, f5
  347. FMA2 f7, f18, f23, f7
  348. FMA1 f8, f16, f24, f8
  349. FMA1 f10, f18, f24, f10
  350. FMA2 f9, f16, f25, f9
  351. FMA2 f11, f18, f25, f11
  352. FMA1 f12, f16, f26, f12
  353. FMA1 f14, f18, f26, f14
  354. FMA2 f13, f16, f27, f13
  355. FMA2 f15, f18, f27, f15
  356. FMA4 f1, f17, f20, f1
  357. FMA4 f3, f19, f20, f3
  358. FMA3 f0, f17, f21, f0
  359. FMA3 f2, f19, f21, f2
  360. FMA4 f5, f17, f22, f5
  361. FMA4 f7, f19, f22, f7
  362. FMA3 f4, f17, f23, f4
  363. FMA3 f6, f19, f23, f6
  364. LFD f20, 8 * SIZE(BO)
  365. LFD f21, 9 * SIZE(BO)
  366. LFD f22, 10 * SIZE(BO)
  367. LFD f23, 11 * SIZE(BO)
  368. FMA4 f9, f17, f24, f9
  369. FMA4 f11, f19, f24, f11
  370. FMA3 f8, f17, f25, f8
  371. FMA3 f10, f19, f25, f10
  372. FMA4 f13, f17, f26, f13
  373. FMA4 f15, f19, f26, f15
  374. FMA3 f12, f17, f27, f12
  375. FMA3 f14, f19, f27, f14
  376. LFD f24, 12 * SIZE(BO)
  377. LFD f25, 13 * SIZE(BO)
  378. LFD f26, 14 * SIZE(BO)
  379. LFD f27, 15 * SIZE(BO)
  380. FMA1 f0, f28, f20, f0
  381. FMA1 f2, f30, f20, f2
  382. FMA2 f1, f28, f21, f1
  383. FMA2 f3, f30, f21, f3
  384. LFD f16, 8 * SIZE(AO)
  385. LFD f17, 9 * SIZE(AO)
  386. LFD f18, 10 * SIZE(AO)
  387. LFD f19, 11 * SIZE(AO)
  388. FMA1 f4, f28, f22, f4
  389. FMA1 f6, f30, f22, f6
  390. FMA2 f5, f28, f23, f5
  391. FMA2 f7, f30, f23, f7
  392. FMA1 f8, f28, f24, f8
  393. FMA1 f10, f30, f24, f10
  394. FMA2 f9, f28, f25, f9
  395. FMA2 f11, f30, f25, f11
  396. FMA1 f12, f28, f26, f12
  397. FMA1 f14, f30, f26, f14
  398. FMA2 f13, f28, f27, f13
  399. FMA2 f15, f30, f27, f15
  400. FMA4 f1, f29, f20, f1
  401. FMA4 f3, f31, f20, f3
  402. FMA3 f0, f29, f21, f0
  403. FMA3 f2, f31, f21, f2
  404. FMA4 f5, f29, f22, f5
  405. FMA4 f7, f31, f22, f7
  406. FMA3 f4, f29, f23, f4
  407. FMA3 f6, f31, f23, f6
  408. LFD f20, 16 * SIZE(BO)
  409. LFD f21, 17 * SIZE(BO)
  410. LFD f22, 18 * SIZE(BO)
  411. LFD f23, 19 * SIZE(BO)
  412. FMA4 f9, f29, f24, f9
  413. FMA4 f11, f31, f24, f11
  414. FMA3 f8, f29, f25, f8
  415. FMA3 f10, f31, f25, f10
  416. FMA4 f13, f29, f26, f13
  417. FMA4 f15, f31, f26, f15
  418. FMA3 f12, f29, f27, f12
  419. FMA3 f14, f31, f27, f14
  420. LFD f24, 20 * SIZE(BO)
  421. LFD f25, 21 * SIZE(BO)
  422. LFD f26, 22 * SIZE(BO)
  423. LFD f27, 23 * SIZE(BO)
  424. FMA1 f0, f16, f20, f0
  425. FMA1 f2, f18, f20, f2
  426. FMA2 f1, f16, f21, f1
  427. FMA2 f3, f18, f21, f3
  428. LFD f28, 12 * SIZE(AO)
  429. LFD f29, 13 * SIZE(AO)
  430. LFD f30, 14 * SIZE(AO)
  431. LFD f31, 15 * SIZE(AO)
  432. FMA1 f4, f16, f22, f4
  433. FMA1 f6, f18, f22, f6
  434. FMA2 f5, f16, f23, f5
  435. FMA2 f7, f18, f23, f7
  436. FMA1 f8, f16, f24, f8
  437. FMA1 f10, f18, f24, f10
  438. FMA2 f9, f16, f25, f9
  439. FMA2 f11, f18, f25, f11
  440. FMA1 f12, f16, f26, f12
  441. FMA1 f14, f18, f26, f14
  442. FMA2 f13, f16, f27, f13
  443. FMA2 f15, f18, f27, f15
  444. FMA4 f1, f17, f20, f1
  445. FMA4 f3, f19, f20, f3
  446. FMA3 f0, f17, f21, f0
  447. FMA3 f2, f19, f21, f2
  448. FMA4 f5, f17, f22, f5
  449. FMA4 f7, f19, f22, f7
  450. FMA3 f4, f17, f23, f4
  451. FMA3 f6, f19, f23, f6
  452. LFD f20, 24 * SIZE(BO)
  453. LFD f21, 25 * SIZE(BO)
  454. LFD f22, 26 * SIZE(BO)
  455. LFD f23, 27 * SIZE(BO)
  456. FMA4 f9, f17, f24, f9
  457. FMA4 f11, f19, f24, f11
  458. FMA3 f8, f17, f25, f8
  459. FMA3 f10, f19, f25, f10
  460. FMA4 f13, f17, f26, f13
  461. FMA4 f15, f19, f26, f15
  462. FMA3 f12, f17, f27, f12
  463. FMA3 f14, f19, f27, f14
  464. LFD f24, 28 * SIZE(BO)
  465. LFD f25, 29 * SIZE(BO)
  466. LFD f26, 30 * SIZE(BO)
  467. LFD f27, 31 * SIZE(BO)
  468. FMA1 f0, f28, f20, f0
  469. FMA1 f2, f30, f20, f2
  470. FMA2 f1, f28, f21, f1
  471. FMA2 f3, f30, f21, f3
  472. LFD f16, 16 * SIZE(AO)
  473. LFD f17, 17 * SIZE(AO)
  474. LFD f18, 18 * SIZE(AO)
  475. LFD f19, 19 * SIZE(AO)
  476. FMA1 f4, f28, f22, f4
  477. FMA1 f6, f30, f22, f6
  478. FMA2 f5, f28, f23, f5
  479. FMA2 f7, f30, f23, f7
  480. FMA1 f8, f28, f24, f8
  481. FMA1 f10, f30, f24, f10
  482. FMA2 f9, f28, f25, f9
  483. FMA2 f11, f30, f25, f11
  484. FMA1 f12, f28, f26, f12
  485. FMA1 f14, f30, f26, f14
  486. FMA2 f13, f28, f27, f13
  487. FMA2 f15, f30, f27, f15
  488. FMA4 f1, f29, f20, f1
  489. FMA4 f3, f31, f20, f3
  490. FMA3 f0, f29, f21, f0
  491. FMA3 f2, f31, f21, f2
  492. FMA4 f5, f29, f22, f5
  493. FMA4 f7, f31, f22, f7
  494. FMA3 f4, f29, f23, f4
  495. FMA3 f6, f31, f23, f6
  496. LFD f20, 32 * SIZE(BO)
  497. LFD f21, 33 * SIZE(BO)
  498. LFD f22, 34 * SIZE(BO)
  499. LFD f23, 35 * SIZE(BO)
  500. FMA4 f9, f29, f24, f9
  501. FMA4 f11, f31, f24, f11
  502. FMA3 f8, f29, f25, f8
  503. FMA3 f10, f31, f25, f10
  504. FMA4 f13, f29, f26, f13
  505. FMA4 f15, f31, f26, f15
  506. FMA3 f12, f29, f27, f12
  507. FMA3 f14, f31, f27, f14
  508. LFD f24, 36 * SIZE(BO)
  509. LFD f25, 37 * SIZE(BO)
  510. LFD f26, 38 * SIZE(BO)
  511. LFD f27, 39 * SIZE(BO)
  512. FMA1 f0, f16, f20, f0
  513. FMA1 f2, f18, f20, f2
  514. FMA2 f1, f16, f21, f1
  515. FMA2 f3, f18, f21, f3
  516. LFD f28, 20 * SIZE(AO)
  517. LFD f29, 21 * SIZE(AO)
  518. LFD f30, 22 * SIZE(AO)
  519. LFD f31, 23 * SIZE(AO)
  520. FMA1 f4, f16, f22, f4
  521. FMA1 f6, f18, f22, f6
  522. FMA2 f5, f16, f23, f5
  523. FMA2 f7, f18, f23, f7
  524. FMA1 f8, f16, f24, f8
  525. FMA1 f10, f18, f24, f10
  526. FMA2 f9, f16, f25, f9
  527. FMA2 f11, f18, f25, f11
  528. FMA1 f12, f16, f26, f12
  529. FMA1 f14, f18, f26, f14
  530. FMA2 f13, f16, f27, f13
  531. FMA2 f15, f18, f27, f15
  532. FMA4 f1, f17, f20, f1
  533. FMA4 f3, f19, f20, f3
  534. FMA3 f0, f17, f21, f0
  535. FMA3 f2, f19, f21, f2
  536. FMA4 f5, f17, f22, f5
  537. FMA4 f7, f19, f22, f7
  538. FMA3 f4, f17, f23, f4
  539. FMA3 f6, f19, f23, f6
  540. LFD f20, 40 * SIZE(BO)
  541. LFD f21, 41 * SIZE(BO)
  542. LFD f22, 42 * SIZE(BO)
  543. LFD f23, 43 * SIZE(BO)
  544. FMA4 f9, f17, f24, f9
  545. FMA4 f11, f19, f24, f11
  546. FMA3 f8, f17, f25, f8
  547. FMA3 f10, f19, f25, f10
  548. FMA4 f13, f17, f26, f13
  549. FMA4 f15, f19, f26, f15
  550. FMA3 f12, f17, f27, f12
  551. FMA3 f14, f19, f27, f14
  552. LFD f24, 44 * SIZE(BO)
  553. LFD f25, 45 * SIZE(BO)
  554. LFD f26, 46 * SIZE(BO)
  555. LFD f27, 47 * SIZE(BO)
  556. FMA1 f0, f28, f20, f0
  557. FMA1 f2, f30, f20, f2
  558. FMA2 f1, f28, f21, f1
  559. FMA2 f3, f30, f21, f3
  560. LFD f16, 24 * SIZE(AO)
  561. LFD f17, 25 * SIZE(AO)
  562. LFD f18, 26 * SIZE(AO)
  563. LFD f19, 27 * SIZE(AO)
  564. FMA1 f4, f28, f22, f4
  565. FMA1 f6, f30, f22, f6
  566. FMA2 f5, f28, f23, f5
  567. FMA2 f7, f30, f23, f7
  568. FMA1 f8, f28, f24, f8
  569. FMA1 f10, f30, f24, f10
  570. FMA2 f9, f28, f25, f9
  571. FMA2 f11, f30, f25, f11
  572. FMA1 f12, f28, f26, f12
  573. FMA1 f14, f30, f26, f14
  574. FMA2 f13, f28, f27, f13
  575. FMA2 f15, f30, f27, f15
  576. FMA4 f1, f29, f20, f1
  577. FMA4 f3, f31, f20, f3
  578. FMA3 f0, f29, f21, f0
  579. FMA3 f2, f31, f21, f2
  580. FMA4 f5, f29, f22, f5
  581. FMA4 f7, f31, f22, f7
  582. FMA3 f4, f29, f23, f4
  583. FMA3 f6, f31, f23, f6
  584. LFD f20, 48 * SIZE(BO)
  585. LFD f21, 49 * SIZE(BO)
  586. LFD f22, 50 * SIZE(BO)
  587. LFD f23, 51 * SIZE(BO)
  588. FMA4 f9, f29, f24, f9
  589. FMA4 f11, f31, f24, f11
  590. FMA3 f8, f29, f25, f8
  591. FMA3 f10, f31, f25, f10
  592. FMA4 f13, f29, f26, f13
  593. FMA4 f15, f31, f26, f15
  594. FMA3 f12, f29, f27, f12
  595. FMA3 f14, f31, f27, f14
  596. LFD f24, 52 * SIZE(BO)
  597. LFD f25, 53 * SIZE(BO)
  598. LFD f26, 54 * SIZE(BO)
  599. LFD f27, 55 * SIZE(BO)
  600. FMA1 f0, f16, f20, f0
  601. FMA1 f2, f18, f20, f2
  602. FMA2 f1, f16, f21, f1
  603. FMA2 f3, f18, f21, f3
  604. LFD f28, 28 * SIZE(AO)
  605. LFD f29, 29 * SIZE(AO)
  606. LFD f30, 30 * SIZE(AO)
  607. LFD f31, 31 * SIZE(AO)
  608. FMA1 f4, f16, f22, f4
  609. FMA1 f6, f18, f22, f6
  610. FMA2 f5, f16, f23, f5
  611. FMA2 f7, f18, f23, f7
  612. FMA1 f8, f16, f24, f8
  613. FMA1 f10, f18, f24, f10
  614. FMA2 f9, f16, f25, f9
  615. FMA2 f11, f18, f25, f11
  616. FMA1 f12, f16, f26, f12
  617. FMA1 f14, f18, f26, f14
  618. FMA2 f13, f16, f27, f13
  619. FMA2 f15, f18, f27, f15
  620. FMA4 f1, f17, f20, f1
  621. FMA4 f3, f19, f20, f3
  622. FMA3 f0, f17, f21, f0
  623. FMA3 f2, f19, f21, f2
  624. FMA4 f5, f17, f22, f5
  625. FMA4 f7, f19, f22, f7
  626. FMA3 f4, f17, f23, f4
  627. FMA3 f6, f19, f23, f6
  628. LFD f20, 56 * SIZE(BO)
  629. LFD f21, 57 * SIZE(BO)
  630. LFD f22, 58 * SIZE(BO)
  631. LFD f23, 59 * SIZE(BO)
  632. FMA4 f9, f17, f24, f9
  633. FMA4 f11, f19, f24, f11
  634. FMA3 f8, f17, f25, f8
  635. FMA3 f10, f19, f25, f10
  636. FMA4 f13, f17, f26, f13
  637. FMA4 f15, f19, f26, f15
  638. FMA3 f12, f17, f27, f12
  639. FMA3 f14, f19, f27, f14
  640. LFD f24, 60 * SIZE(BO)
  641. LFD f25, 61 * SIZE(BO)
  642. LFD f26, 62 * SIZE(BO)
  643. LFD f27, 63 * SIZE(BO)
  644. FMA1 f0, f28, f20, f0
  645. FMA1 f2, f30, f20, f2
  646. FMA2 f1, f28, f21, f1
  647. FMA2 f3, f30, f21, f3
  648. LFD f16, 32 * SIZE(AO)
  649. LFD f17, 33 * SIZE(AO)
  650. LFD f18, 34 * SIZE(AO)
  651. LFD f19, 35 * SIZE(AO)
  652. FMA1 f4, f28, f22, f4
  653. FMA1 f6, f30, f22, f6
  654. FMA2 f5, f28, f23, f5
  655. FMA2 f7, f30, f23, f7
  656. FMA1 f8, f28, f24, f8
  657. FMA1 f10, f30, f24, f10
  658. FMA2 f9, f28, f25, f9
  659. FMA2 f11, f30, f25, f11
  660. FMA1 f12, f28, f26, f12
  661. FMA1 f14, f30, f26, f14
  662. FMA2 f13, f28, f27, f13
  663. FMA2 f15, f30, f27, f15
  664. FMA4 f1, f29, f20, f1
  665. FMA4 f3, f31, f20, f3
  666. FMA3 f0, f29, f21, f0
  667. FMA3 f2, f31, f21, f2
  668. FMA4 f5, f29, f22, f5
  669. FMA4 f7, f31, f22, f7
  670. FMA3 f4, f29, f23, f4
  671. FMA3 f6, f31, f23, f6
  672. LFD f20, 64 * SIZE(BO)
  673. LFD f21, 65 * SIZE(BO)
  674. LFD f22, 66 * SIZE(BO)
  675. LFD f23, 67 * SIZE(BO)
  676. FMA4 f9, f29, f24, f9
  677. FMA4 f11, f31, f24, f11
  678. FMA3 f8, f29, f25, f8
  679. FMA3 f10, f31, f25, f10
  680. FMA4 f13, f29, f26, f13
  681. FMA4 f15, f31, f26, f15
  682. FMA3 f12, f29, f27, f12
  683. FMA3 f14, f31, f27, f14
  684. LFD f24, 68 * SIZE(BO)
  685. LFD f25, 69 * SIZE(BO)
  686. LFD f26, 70 * SIZE(BO)
  687. LFD f27, 71 * SIZE(BO)
  688. addi AO, AO, 32 * SIZE
  689. addi BO, BO, 64 * SIZE
  690. bdnz LL(12)
  691. .align 4
  692. LL(15):
  693. lfd f30, ALPHA_R
  694. lfd f31, ALPHA_I
  695. dcbtst B, BB
  696. addi BB, BB, 16 * SIZE
  697. dcbtst B, BB
  698. addi BB, BB, 16 * SIZE
  699. #ifndef TRMMKERNEL
  700. andi. r0, K, 7
  701. mtspr CTR, r0
  702. ble LL(18)
  703. #else
  704. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  705. sub TEMP, K, KK
  706. #elif defined(LEFT)
  707. addi TEMP, KK, 2
  708. #else
  709. addi TEMP, KK, 4
  710. #endif
  711. andi. TEMP, TEMP, 7
  712. mtspr CTR, TEMP
  713. ble LL(18)
  714. #endif
  715. .align 4
  716. LL(16):
  717. FMA1 f0, f16, f20, f0
  718. FMA1 f2, f18, f20, f2
  719. FMA2 f1, f16, f21, f1
  720. FMA2 f3, f18, f21, f3
  721. FMA1 f4, f16, f22, f4
  722. FMA1 f6, f18, f22, f6
  723. FMA2 f5, f16, f23, f5
  724. FMA2 f7, f18, f23, f7
  725. FMA1 f8, f16, f24, f8
  726. FMA1 f10, f18, f24, f10
  727. FMA2 f9, f16, f25, f9
  728. FMA2 f11, f18, f25, f11
  729. FMA1 f12, f16, f26, f12
  730. FMA1 f14, f18, f26, f14
  731. FMA2 f13, f16, f27, f13
  732. FMA2 f15, f18, f27, f15
  733. FMA4 f1, f17, f20, f1
  734. FMA4 f3, f19, f20, f3
  735. FMA3 f0, f17, f21, f0
  736. FMA3 f2, f19, f21, f2
  737. FMA4 f5, f17, f22, f5
  738. FMA4 f7, f19, f22, f7
  739. FMA3 f4, f17, f23, f4
  740. FMA3 f6, f19, f23, f6
  741. FMA4 f9, f17, f24, f9
  742. FMA4 f11, f19, f24, f11
  743. FMA3 f8, f17, f25, f8
  744. FMA3 f10, f19, f25, f10
  745. FMA4 f13, f17, f26, f13
  746. FMA4 f15, f19, f26, f15
  747. FMA3 f12, f17, f27, f12
  748. FMA3 f14, f19, f27, f14
  749. LFD f16, 4 * SIZE(AO)
  750. LFD f17, 5 * SIZE(AO)
  751. LFD f18, 6 * SIZE(AO)
  752. LFD f19, 7 * SIZE(AO)
  753. LFD f20, 8 * SIZE(BO)
  754. LFD f21, 9 * SIZE(BO)
  755. LFD f22, 10 * SIZE(BO)
  756. LFD f23, 11 * SIZE(BO)
  757. LFD f24, 12 * SIZE(BO)
  758. LFD f25, 13 * SIZE(BO)
  759. LFD f26, 14 * SIZE(BO)
  760. LFD f27, 15 * SIZE(BO)
  761. addi AO, AO, 4 * SIZE
  762. addi BO, BO, 8 * SIZE
  763. bdnz LL(16)
  764. .align 4
  765. LL(18):
  766. #ifndef TRMMKERNEL
  767. LFD f16, 0 * SIZE(CO1)
  768. LFD f17, 1 * SIZE(CO1)
  769. LFD f18, 2 * SIZE(CO1)
  770. LFD f19, 3 * SIZE(CO1)
  771. LFD f20, 0 * SIZE(CO2)
  772. LFD f21, 1 * SIZE(CO2)
  773. LFD f22, 2 * SIZE(CO2)
  774. LFD f23, 3 * SIZE(CO2)
  775. FNMSUB f24, f31, f1, f16
  776. FMADD f25, f31, f0, f17
  777. FNMSUB f26, f31, f3, f18
  778. FMADD f27, f31, f2, f19
  779. LFD f16, 0 * SIZE(CO3)
  780. LFD f17, 1 * SIZE(CO3)
  781. LFD f18, 2 * SIZE(CO3)
  782. LFD f19, 3 * SIZE(CO3)
  783. FMADD f0, f30, f0, f24
  784. FMADD f1, f30, f1, f25
  785. FMADD f2, f30, f2, f26
  786. FMADD f3, f30, f3, f27
  787. FNMSUB f24, f31, f5, f20
  788. FMADD f25, f31, f4, f21
  789. FNMSUB f26, f31, f7, f22
  790. FMADD f27, f31, f6, f23
  791. LFD f20, 0 * SIZE(CO4)
  792. LFD f21, 1 * SIZE(CO4)
  793. LFD f22, 2 * SIZE(CO4)
  794. LFD f23, 3 * SIZE(CO4)
  795. FMADD f4, f30, f4, f24
  796. FMADD f5, f30, f5, f25
  797. FMADD f6, f30, f6, f26
  798. FMADD f7, f30, f7, f27
  799. FNMSUB f24, f31, f9, f16
  800. FMADD f25, f31, f8, f17
  801. FNMSUB f26, f31, f11, f18
  802. FMADD f27, f31, f10, f19
  803. FMADD f8, f30, f8, f24
  804. FMADD f9, f30, f9, f25
  805. FMADD f10, f30, f10, f26
  806. FMADD f11, f30, f11, f27
  807. FNMSUB f24, f31, f13, f20
  808. FMADD f25, f31, f12, f21
  809. FNMSUB f26, f31, f15, f22
  810. FMADD f27, f31, f14, f23
  811. FMADD f12, f30, f12, f24
  812. FMADD f13, f30, f13, f25
  813. FMADD f14, f30, f14, f26
  814. FMADD f15, f30, f15, f27
  815. #else
  816. FMUL f16, f31, f1
  817. FMUL f17, f31, f0
  818. FMUL f18, f31, f3
  819. FMUL f19, f31, f2
  820. FMUL f20, f31, f5
  821. FMUL f21, f31, f4
  822. FMUL f22, f31, f7
  823. FMUL f23, f31, f6
  824. FMSUB f0, f30, f0, f16
  825. FMADD f1, f30, f1, f17
  826. FMADD f2, f30, f2, f18
  827. FMADD f3, f30, f3, f19
  828. FMSUB f4, f30, f4, f20
  829. FMADD f5, f30, f5, f21
  830. FMADD f6, f30, f6, f22
  831. FMADD f7, f30, f7, f23
  832. FMUL f16, f31, f9
  833. FMUL f17, f31, f8
  834. FMUL f18, f31, f11
  835. FMUL f19, f31, f10
  836. FMUL f20, f31, f13
  837. FMUL f21, f31, f12
  838. FMUL f22, f31, f15
  839. FMUL f23, f31, f14
  840. FMSUB f8, f30, f8, f16
  841. FMADD f9, f30, f9, f17
  842. FMADD f10, f30, f10, f18
  843. FMADD f11, f30, f11, f19
  844. FMSUB f12, f30, f12, f20
  845. FMADD f13, f30, f13, f21
  846. FMADD f14, f30, f14, f22
  847. FMADD f15, f30, f15, f23
  848. #endif
  849. STFD f0, 0 * SIZE(CO1)
  850. STFD f1, 1 * SIZE(CO1)
  851. STFD f2, 2 * SIZE(CO1)
  852. STFD f3, 3 * SIZE(CO1)
  853. lfs f0, FZERO
  854. fmr f1, f0
  855. fmr f2, f0
  856. fmr f3, f0
  857. STFD f4, 0 * SIZE(CO2)
  858. STFD f5, 1 * SIZE(CO2)
  859. STFD f6, 2 * SIZE(CO2)
  860. STFD f7, 3 * SIZE(CO2)
  861. fmr f4, f0
  862. fmr f5, f0
  863. fmr f6, f0
  864. fmr f7, f0
  865. STFD f8, 0 * SIZE(CO3)
  866. STFD f9, 1 * SIZE(CO3)
  867. STFD f10, 2 * SIZE(CO3)
  868. STFD f11, 3 * SIZE(CO3)
  869. fmr f8, f0
  870. fmr f9, f0
  871. fmr f10, f0
  872. fmr f11, f0
  873. STFD f12, 0 * SIZE(CO4)
  874. STFD f13, 1 * SIZE(CO4)
  875. STFD f14, 2 * SIZE(CO4)
  876. STFD f15, 3 * SIZE(CO4)
  877. fmr f12, f0
  878. fmr f13, f0
  879. fmr f14, f0
  880. fmr f15, f0
  881. addi CO1, CO1, 4 * SIZE
  882. addi CO2, CO2, 4 * SIZE
  883. addi CO3, CO3, 4 * SIZE
  884. addi CO4, CO4, 4 * SIZE
  885. #ifdef TRMMKERNEL
  886. #if ( defined(LEFT) && defined(TRANSA)) || \
  887. (!defined(LEFT) && !defined(TRANSA))
  888. sub TEMP, K, KK
  889. #ifdef LEFT
  890. addi TEMP, TEMP, -2
  891. #else
  892. addi TEMP, TEMP, -4
  893. #endif
  894. slwi r0, TEMP, 1 + ZBASE_SHIFT
  895. slwi TEMP, TEMP, 2 + ZBASE_SHIFT
  896. add AO, AO, r0
  897. add BO, BO, TEMP
  898. #endif
  899. #ifdef LEFT
  900. addi KK, KK, 2
  901. #endif
  902. #endif
  903. addic. I, I, -1
  904. bgt LL(11)
  905. .align 4
  906. LL(20):
  907. andi. I, M, 1
  908. ble LL(29)
  909. #ifndef TRMMKERNEL
  910. LFD f16, 0 * SIZE(AO)
  911. LFD f17, 1 * SIZE(AO)
  912. LFD f18, 2 * SIZE(AO)
  913. LFD f19, 3 * SIZE(AO)
  914. LFD f20, 0 * SIZE(B)
  915. LFD f21, 1 * SIZE(B)
  916. LFD f22, 2 * SIZE(B)
  917. LFD f23, 3 * SIZE(B)
  918. LFD f24, 4 * SIZE(B)
  919. LFD f25, 5 * SIZE(B)
  920. LFD f26, 6 * SIZE(B)
  921. LFD f27, 7 * SIZE(B)
  922. srawi. r0, K, 2
  923. mr BO, B
  924. mtspr CTR, r0
  925. ble LL(25)
  926. #else
  927. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  928. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  929. LFD f16, 0 * SIZE(AO)
  930. LFD f17, 1 * SIZE(AO)
  931. LFD f18, 2 * SIZE(AO)
  932. LFD f19, 3 * SIZE(AO)
  933. LFD f20, 0 * SIZE(B)
  934. LFD f21, 1 * SIZE(B)
  935. LFD f22, 2 * SIZE(B)
  936. LFD f23, 3 * SIZE(B)
  937. LFD f24, 4 * SIZE(B)
  938. LFD f25, 5 * SIZE(B)
  939. LFD f26, 6 * SIZE(B)
  940. LFD f27, 7 * SIZE(B)
  941. mr BO, B
  942. #else
  943. slwi r0, KK, 0 + ZBASE_SHIFT
  944. slwi TEMP, KK, 2 + ZBASE_SHIFT
  945. add AO, AO, r0
  946. add BO, B, TEMP
  947. LFD f16, 0 * SIZE(AO)
  948. LFD f17, 1 * SIZE(AO)
  949. LFD f18, 2 * SIZE(AO)
  950. LFD f19, 3 * SIZE(AO)
  951. LFD f20, 0 * SIZE(BO)
  952. LFD f21, 1 * SIZE(BO)
  953. LFD f22, 2 * SIZE(BO)
  954. LFD f23, 3 * SIZE(BO)
  955. LFD f24, 4 * SIZE(BO)
  956. LFD f25, 5 * SIZE(BO)
  957. LFD f26, 6 * SIZE(BO)
  958. LFD f27, 7 * SIZE(BO)
  959. #endif
  960. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  961. sub TEMP, K, KK
  962. #elif defined(LEFT)
  963. addi TEMP, KK, 1
  964. #else
  965. addi TEMP, KK, 4
  966. #endif
  967. srawi. TEMP, TEMP, 2
  968. mtspr CTR, TEMP
  969. ble LL(25)
  970. #endif
  971. .align 4
  972. LL(22):
  973. FMA1 f0, f16, f20, f0
  974. FMA4 f3, f17, f20, f3
  975. FMA2 f1, f16, f21, f1
  976. FMA3 f2, f17, f21, f2
  977. LFD f28, 4 * SIZE(AO)
  978. LFD f29, 5 * SIZE(AO)
  979. LFD f30, 6 * SIZE(AO)
  980. LFD f31, 7 * SIZE(AO)
  981. FMA1 f4, f16, f22, f4
  982. FMA4 f7, f17, f22, f7
  983. FMA2 f5, f16, f23, f5
  984. FMA3 f6, f17, f23, f6
  985. LFD f20, 8 * SIZE(BO)
  986. LFD f21, 9 * SIZE(BO)
  987. LFD f22, 10 * SIZE(BO)
  988. LFD f23, 11 * SIZE(BO)
  989. FMA1 f8, f16, f24, f8
  990. FMA4 f11, f17, f24, f11
  991. FMA2 f9, f16, f25, f9
  992. FMA3 f10, f17, f25, f10
  993. FMA1 f12, f16, f26, f12
  994. FMA4 f15, f17, f26, f15
  995. FMA2 f13, f16, f27, f13
  996. FMA3 f14, f17, f27, f14
  997. LFD f24, 12 * SIZE(BO)
  998. LFD f25, 13 * SIZE(BO)
  999. LFD f26, 14 * SIZE(BO)
  1000. LFD f27, 15 * SIZE(BO)
  1001. FMA1 f0, f18, f20, f0
  1002. FMA4 f3, f19, f20, f3
  1003. FMA2 f1, f18, f21, f1
  1004. FMA3 f2, f19, f21, f2
  1005. FMA1 f4, f18, f22, f4
  1006. FMA4 f7, f19, f22, f7
  1007. FMA2 f5, f18, f23, f5
  1008. FMA3 f6, f19, f23, f6
  1009. LFD f20, 16 * SIZE(BO)
  1010. LFD f21, 17 * SIZE(BO)
  1011. LFD f22, 18 * SIZE(BO)
  1012. LFD f23, 19 * SIZE(BO)
  1013. FMA1 f8, f18, f24, f8
  1014. FMA4 f11, f19, f24, f11
  1015. FMA2 f9, f18, f25, f9
  1016. FMA3 f10, f19, f25, f10
  1017. FMA1 f12, f18, f26, f12
  1018. FMA4 f15, f19, f26, f15
  1019. FMA2 f13, f18, f27, f13
  1020. FMA3 f14, f19, f27, f14
  1021. LFD f24, 20 * SIZE(BO)
  1022. LFD f25, 21 * SIZE(BO)
  1023. LFD f26, 22 * SIZE(BO)
  1024. LFD f27, 23 * SIZE(BO)
  1025. FMA1 f0, f28, f20, f0
  1026. FMA4 f3, f29, f20, f3
  1027. FMA2 f1, f28, f21, f1
  1028. FMA3 f2, f29, f21, f2
  1029. LFD f16, 8 * SIZE(AO)
  1030. LFD f17, 9 * SIZE(AO)
  1031. LFD f18, 10 * SIZE(AO)
  1032. LFD f19, 11 * SIZE(AO)
  1033. FMA1 f4, f28, f22, f4
  1034. FMA4 f7, f29, f22, f7
  1035. FMA2 f5, f28, f23, f5
  1036. FMA3 f6, f29, f23, f6
  1037. LFD f20, 24 * SIZE(BO)
  1038. LFD f21, 25 * SIZE(BO)
  1039. LFD f22, 26 * SIZE(BO)
  1040. LFD f23, 27 * SIZE(BO)
  1041. FMA1 f8, f28, f24, f8
  1042. FMA4 f11, f29, f24, f11
  1043. FMA2 f9, f28, f25, f9
  1044. FMA3 f10, f29, f25, f10
  1045. FMA1 f12, f28, f26, f12
  1046. FMA4 f15, f29, f26, f15
  1047. FMA2 f13, f28, f27, f13
  1048. FMA3 f14, f29, f27, f14
  1049. LFD f24, 28 * SIZE(BO)
  1050. LFD f25, 29 * SIZE(BO)
  1051. LFD f26, 30 * SIZE(BO)
  1052. LFD f27, 31 * SIZE(BO)
  1053. FMA1 f0, f30, f20, f0
  1054. FMA4 f3, f31, f20, f3
  1055. FMA2 f1, f30, f21, f1
  1056. FMA3 f2, f31, f21, f2
  1057. FMA1 f4, f30, f22, f4
  1058. FMA4 f7, f31, f22, f7
  1059. FMA2 f5, f30, f23, f5
  1060. FMA3 f6, f31, f23, f6
  1061. LFD f20, 32 * SIZE(BO)
  1062. LFD f21, 33 * SIZE(BO)
  1063. LFD f22, 34 * SIZE(BO)
  1064. LFD f23, 35 * SIZE(BO)
  1065. FMA1 f8, f30, f24, f8
  1066. FMA4 f11, f31, f24, f11
  1067. FMA2 f9, f30, f25, f9
  1068. FMA3 f10, f31, f25, f10
  1069. FMA1 f12, f30, f26, f12
  1070. FMA4 f15, f31, f26, f15
  1071. FMA2 f13, f30, f27, f13
  1072. FMA3 f14, f31, f27, f14
  1073. LFD f24, 36 * SIZE(BO)
  1074. LFD f25, 37 * SIZE(BO)
  1075. LFD f26, 38 * SIZE(BO)
  1076. LFD f27, 39 * SIZE(BO)
  1077. addi AO, AO, 8 * SIZE
  1078. addi BO, BO, 32 * SIZE
  1079. bdnz LL(22)
  1080. .align 4
  1081. LL(25):
  1082. lfd f30, ALPHA_R
  1083. lfd f31, ALPHA_I
  1084. #ifndef TRMMKERNEL
  1085. andi. r0, K, 3
  1086. mtspr CTR, r0
  1087. ble LL(28)
  1088. #else
  1089. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1090. sub TEMP, K, KK
  1091. #elif defined(LEFT)
  1092. addi TEMP, KK, 1
  1093. #else
  1094. addi TEMP, KK, 4
  1095. #endif
  1096. andi. TEMP, TEMP, 3
  1097. mtspr CTR, TEMP
  1098. ble LL(28)
  1099. #endif
  1100. .align 4
  1101. LL(26):
  1102. FMA1 f0, f16, f20, f0
  1103. FMA4 f3, f17, f20, f3
  1104. FMA2 f1, f16, f21, f1
  1105. FMA3 f2, f17, f21, f2
  1106. FMA1 f4, f16, f22, f4
  1107. FMA4 f7, f17, f22, f7
  1108. FMA2 f5, f16, f23, f5
  1109. FMA3 f6, f17, f23, f6
  1110. LFD f20, 8 * SIZE(BO)
  1111. LFD f21, 9 * SIZE(BO)
  1112. LFD f22, 10 * SIZE(BO)
  1113. LFD f23, 11 * SIZE(BO)
  1114. FMA1 f8, f16, f24, f8
  1115. FMA4 f11, f17, f24, f11
  1116. FMA2 f9, f16, f25, f9
  1117. FMA3 f10, f17, f25, f10
  1118. FMA1 f12, f16, f26, f12
  1119. FMA4 f15, f17, f26, f15
  1120. FMA2 f13, f16, f27, f13
  1121. FMA3 f14, f17, f27, f14
  1122. LFD f16, 2 * SIZE(AO)
  1123. LFD f17, 3 * SIZE(AO)
  1124. LFD f24, 12 * SIZE(BO)
  1125. LFD f25, 13 * SIZE(BO)
  1126. LFD f26, 14 * SIZE(BO)
  1127. LFD f27, 15 * SIZE(BO)
  1128. addi AO, AO, 2 * SIZE
  1129. addi BO, BO, 8 * SIZE
  1130. bdnz LL(26)
  1131. .align 4
  1132. LL(28):
  1133. #ifndef TRMMKERNEL
  1134. LFD f16, 0 * SIZE(CO1)
  1135. LFD f17, 1 * SIZE(CO1)
  1136. LFD f18, 0 * SIZE(CO2)
  1137. LFD f19, 1 * SIZE(CO2)
  1138. FADD f0, f0, f2
  1139. FADD f1, f1, f3
  1140. FADD f4, f4, f6
  1141. FADD f5, f5, f7
  1142. LFD f20, 0 * SIZE(CO3)
  1143. LFD f21, 1 * SIZE(CO3)
  1144. LFD f22, 0 * SIZE(CO4)
  1145. LFD f23, 1 * SIZE(CO4)
  1146. FADD f8, f8, f10
  1147. FADD f9, f9, f11
  1148. FADD f12, f12, f14
  1149. FADD f13, f13, f15
  1150. FNMSUB f24, f31, f1, f16
  1151. FMADD f25, f31, f0, f17
  1152. FNMSUB f26, f31, f5, f18
  1153. FMADD f27, f31, f4, f19
  1154. FMADD f0, f30, f0, f24
  1155. FMADD f1, f30, f1, f25
  1156. FMADD f4, f30, f4, f26
  1157. FMADD f5, f30, f5, f27
  1158. FNMSUB f24, f31, f9, f20
  1159. FMADD f25, f31, f8, f21
  1160. FNMSUB f26, f31, f13, f22
  1161. FMADD f27, f31, f12, f23
  1162. FMADD f8, f30, f8, f24
  1163. FMADD f9, f30, f9, f25
  1164. FMADD f12, f30, f12, f26
  1165. FMADD f13, f30, f13, f27
  1166. #else
  1167. FADD f0, f0, f2
  1168. FADD f1, f1, f3
  1169. FADD f4, f4, f6
  1170. FADD f5, f5, f7
  1171. FMUL f16, f31, f1
  1172. FMUL f17, f31, f0
  1173. FMUL f18, f31, f5
  1174. FMUL f19, f31, f4
  1175. FMSUB f0, f30, f0, f16
  1176. FMADD f1, f30, f1, f17
  1177. FMSUB f4, f30, f4, f18
  1178. FMADD f5, f30, f5, f19
  1179. FADD f8, f8, f10
  1180. FADD f9, f9, f11
  1181. FADD f12, f12, f14
  1182. FADD f13, f13, f15
  1183. FMUL f20, f31, f9
  1184. FMUL f21, f31, f8
  1185. FMUL f22, f31, f13
  1186. FMUL f23, f31, f12
  1187. FMSUB f8, f30, f8, f20
  1188. FMADD f9, f30, f9, f21
  1189. FMSUB f12, f30, f12, f22
  1190. FMADD f13, f30, f13, f23
  1191. #endif
  1192. STFD f0, 0 * SIZE(CO1)
  1193. STFD f1, 1 * SIZE(CO1)
  1194. STFD f4, 0 * SIZE(CO2)
  1195. STFD f5, 1 * SIZE(CO2)
  1196. STFD f8, 0 * SIZE(CO3)
  1197. STFD f9, 1 * SIZE(CO3)
  1198. STFD f12, 0 * SIZE(CO4)
  1199. STFD f13, 1 * SIZE(CO4)
  1200. addi CO1, CO1, 2 * SIZE
  1201. addi CO2, CO2, 2 * SIZE
  1202. addi CO3, CO3, 2 * SIZE
  1203. addi CO4, CO4, 2 * SIZE
  1204. #ifdef TRMMKERNEL
  1205. #if ( defined(LEFT) && defined(TRANSA)) || \
  1206. (!defined(LEFT) && !defined(TRANSA))
  1207. sub TEMP, K, KK
  1208. #ifdef LEFT
  1209. addi TEMP, TEMP, -1
  1210. #else
  1211. addi TEMP, TEMP, -4
  1212. #endif
  1213. slwi r0, TEMP, 0 + ZBASE_SHIFT
  1214. slwi TEMP, TEMP, 2 + ZBASE_SHIFT
  1215. add AO, AO, r0
  1216. add BO, BO, TEMP
  1217. #endif
  1218. #ifdef LEFT
  1219. addi KK, KK, 1
  1220. #endif
  1221. #endif
  1222. .align 4
  1223. LL(29):
  1224. #if defined(TRMMKERNEL) && !defined(LEFT)
  1225. addi KK, KK, 4
  1226. #endif
  1227. mr B, BO
  1228. addic. J, J, -1
  1229. bgt LL(10)
  1230. .align 4
  1231. LL(30):
  1232. andi. J, N, 2
  1233. ble LL(50)
  1234. mr CO1, C
  1235. add CO2, C, LDC
  1236. add C, CO2, LDC
  1237. #if defined(TRMMKERNEL) && defined(LEFT)
  1238. mr KK, OFFSET
  1239. #endif
  1240. slwi BB, K, ZBASE_SHIFT + 1
  1241. mr AO, A
  1242. lfs f0, FZERO
  1243. fmr f1, f0
  1244. fmr f2, f0
  1245. fmr f3, f0
  1246. fmr f4, f0
  1247. fmr f5, f0
  1248. fmr f6, f0
  1249. fmr f7, f0
  1250. fmr f8, f0
  1251. fmr f9, f0
  1252. fmr f10, f0
  1253. fmr f11, f0
  1254. fmr f12, f0
  1255. fmr f13, f0
  1256. fmr f14, f0
  1257. fmr f15, f0
  1258. srawi. I, M, 1
  1259. ble LL(40)
  1260. .align 4
  1261. LL(31):
  1262. #ifndef TRMMKERNEL
  1263. LFD f16, 0 * SIZE(AO)
  1264. LFD f17, 1 * SIZE(AO)
  1265. LFD f18, 2 * SIZE(AO)
  1266. LFD f19, 3 * SIZE(AO)
  1267. LFD f20, 0 * SIZE(B)
  1268. LFD f21, 1 * SIZE(B)
  1269. LFD f22, 2 * SIZE(B)
  1270. LFD f23, 3 * SIZE(B)
  1271. LFD f24, 4 * SIZE(B)
  1272. LFD f25, 5 * SIZE(B)
  1273. LFD f26, 6 * SIZE(B)
  1274. LFD f27, 7 * SIZE(B)
  1275. dcbtst CO1, PREC
  1276. dcbtst CO2, PREC
  1277. srawi. r0, K, 3
  1278. mr BO, B
  1279. mtspr CTR, r0
  1280. ble LL(35)
  1281. #else
  1282. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  1283. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  1284. LFD f16, 0 * SIZE(AO)
  1285. LFD f17, 1 * SIZE(AO)
  1286. LFD f18, 2 * SIZE(AO)
  1287. LFD f19, 3 * SIZE(AO)
  1288. LFD f20, 0 * SIZE(B)
  1289. LFD f21, 1 * SIZE(B)
  1290. LFD f22, 2 * SIZE(B)
  1291. LFD f23, 3 * SIZE(B)
  1292. LFD f24, 4 * SIZE(B)
  1293. LFD f25, 5 * SIZE(B)
  1294. LFD f26, 6 * SIZE(B)
  1295. LFD f27, 7 * SIZE(B)
  1296. mr BO, B
  1297. #else
  1298. slwi r0, KK, 1 + ZBASE_SHIFT
  1299. slwi TEMP, KK, 1 + ZBASE_SHIFT
  1300. add AO, AO, r0
  1301. add BO, B, TEMP
  1302. LFD f16, 0 * SIZE(AO)
  1303. LFD f17, 1 * SIZE(AO)
  1304. LFD f18, 2 * SIZE(AO)
  1305. LFD f19, 3 * SIZE(AO)
  1306. LFD f20, 0 * SIZE(BO)
  1307. LFD f21, 1 * SIZE(BO)
  1308. LFD f22, 2 * SIZE(BO)
  1309. LFD f23, 3 * SIZE(BO)
  1310. LFD f24, 4 * SIZE(BO)
  1311. LFD f25, 5 * SIZE(BO)
  1312. LFD f26, 6 * SIZE(BO)
  1313. LFD f27, 7 * SIZE(BO)
  1314. #endif
  1315. dcbtst CO1, PREC
  1316. dcbtst CO2, PREC
  1317. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1318. sub TEMP, K, KK
  1319. #elif defined(LEFT)
  1320. addi TEMP, KK, 2
  1321. #else
  1322. addi TEMP, KK, 2
  1323. #endif
  1324. srawi. TEMP, TEMP, 3
  1325. mtspr CTR, TEMP
  1326. ble LL(35)
  1327. #endif
  1328. .align 4
  1329. LL(32):
  1330. dcbt AO, PREA
  1331. dcbtst BO, PREA
  1332. FMA1 f0, f16, f20, f0
  1333. FMA1 f2, f18, f20, f2
  1334. FMA2 f1, f16, f21, f1
  1335. FMA2 f3, f18, f21, f3
  1336. LFD f28, 4 * SIZE(AO)
  1337. LFD f29, 5 * SIZE(AO)
  1338. LFD f30, 6 * SIZE(AO)
  1339. LFD f31, 7 * SIZE(AO)
  1340. FMA1 f4, f16, f22, f4
  1341. FMA1 f6, f18, f22, f6
  1342. FMA2 f5, f16, f23, f5
  1343. FMA2 f7, f18, f23, f7
  1344. FMA4 f9, f17, f20, f9
  1345. FMA4 f11, f19, f20, f11
  1346. FMA3 f8, f17, f21, f8
  1347. FMA3 f10, f19, f21, f10
  1348. FMA4 f13, f17, f22, f13
  1349. FMA4 f15, f19, f22, f15
  1350. FMA3 f12, f17, f23, f12
  1351. FMA3 f14, f19, f23, f14
  1352. LFD f20, 8 * SIZE(BO)
  1353. LFD f21, 9 * SIZE(BO)
  1354. LFD f22, 10 * SIZE(BO)
  1355. LFD f23, 11 * SIZE(BO)
  1356. FMA1 f0, f28, f24, f0
  1357. FMA1 f2, f30, f24, f2
  1358. FMA2 f1, f28, f25, f1
  1359. FMA2 f3, f30, f25, f3
  1360. LFD f16, 8 * SIZE(AO)
  1361. LFD f17, 9 * SIZE(AO)
  1362. LFD f18, 10 * SIZE(AO)
  1363. LFD f19, 11 * SIZE(AO)
  1364. FMA1 f4, f28, f26, f4
  1365. FMA1 f6, f30, f26, f6
  1366. FMA2 f5, f28, f27, f5
  1367. FMA2 f7, f30, f27, f7
  1368. FMA4 f9, f29, f24, f9
  1369. FMA4 f11, f31, f24, f11
  1370. FMA3 f8, f29, f25, f8
  1371. FMA3 f10, f31, f25, f10
  1372. FMA4 f13, f29, f26, f13
  1373. FMA4 f15, f31, f26, f15
  1374. FMA3 f12, f29, f27, f12
  1375. FMA3 f14, f31, f27, f14
  1376. LFD f24, 12 * SIZE(BO)
  1377. LFD f25, 13 * SIZE(BO)
  1378. LFD f26, 14 * SIZE(BO)
  1379. LFD f27, 15 * SIZE(BO)
  1380. FMA1 f0, f16, f20, f0
  1381. FMA1 f2, f18, f20, f2
  1382. FMA2 f1, f16, f21, f1
  1383. FMA2 f3, f18, f21, f3
  1384. LFD f28, 12 * SIZE(AO)
  1385. LFD f29, 13 * SIZE(AO)
  1386. LFD f30, 14 * SIZE(AO)
  1387. LFD f31, 15 * SIZE(AO)
  1388. FMA1 f4, f16, f22, f4
  1389. FMA1 f6, f18, f22, f6
  1390. FMA2 f5, f16, f23, f5
  1391. FMA2 f7, f18, f23, f7
  1392. FMA4 f9, f17, f20, f9
  1393. FMA4 f11, f19, f20, f11
  1394. FMA3 f8, f17, f21, f8
  1395. FMA3 f10, f19, f21, f10
  1396. FMA4 f13, f17, f22, f13
  1397. FMA4 f15, f19, f22, f15
  1398. FMA3 f12, f17, f23, f12
  1399. FMA3 f14, f19, f23, f14
  1400. LFD f20, 16 * SIZE(BO)
  1401. LFD f21, 17 * SIZE(BO)
  1402. LFD f22, 18 * SIZE(BO)
  1403. LFD f23, 19 * SIZE(BO)
  1404. FMA1 f0, f28, f24, f0
  1405. FMA1 f2, f30, f24, f2
  1406. FMA2 f1, f28, f25, f1
  1407. FMA2 f3, f30, f25, f3
  1408. LFD f16, 16 * SIZE(AO)
  1409. LFD f17, 17 * SIZE(AO)
  1410. LFD f18, 18 * SIZE(AO)
  1411. LFD f19, 19 * SIZE(AO)
  1412. FMA1 f4, f28, f26, f4
  1413. FMA1 f6, f30, f26, f6
  1414. FMA2 f5, f28, f27, f5
  1415. FMA2 f7, f30, f27, f7
  1416. FMA4 f9, f29, f24, f9
  1417. FMA4 f11, f31, f24, f11
  1418. FMA3 f8, f29, f25, f8
  1419. FMA3 f10, f31, f25, f10
  1420. FMA4 f13, f29, f26, f13
  1421. FMA4 f15, f31, f26, f15
  1422. FMA3 f12, f29, f27, f12
  1423. FMA3 f14, f31, f27, f14
  1424. LFD f24, 20 * SIZE(BO)
  1425. LFD f25, 21 * SIZE(BO)
  1426. LFD f26, 22 * SIZE(BO)
  1427. LFD f27, 23 * SIZE(BO)
  1428. FMA1 f0, f16, f20, f0
  1429. FMA1 f2, f18, f20, f2
  1430. FMA2 f1, f16, f21, f1
  1431. FMA2 f3, f18, f21, f3
  1432. LFD f28, 20 * SIZE(AO)
  1433. LFD f29, 21 * SIZE(AO)
  1434. LFD f30, 22 * SIZE(AO)
  1435. LFD f31, 23 * SIZE(AO)
  1436. FMA1 f4, f16, f22, f4
  1437. FMA1 f6, f18, f22, f6
  1438. FMA2 f5, f16, f23, f5
  1439. FMA2 f7, f18, f23, f7
  1440. FMA4 f9, f17, f20, f9
  1441. FMA4 f11, f19, f20, f11
  1442. FMA3 f8, f17, f21, f8
  1443. FMA3 f10, f19, f21, f10
  1444. FMA4 f13, f17, f22, f13
  1445. FMA4 f15, f19, f22, f15
  1446. FMA3 f12, f17, f23, f12
  1447. FMA3 f14, f19, f23, f14
  1448. LFD f20, 24 * SIZE(BO)
  1449. LFD f21, 25 * SIZE(BO)
  1450. LFD f22, 26 * SIZE(BO)
  1451. LFD f23, 27 * SIZE(BO)
  1452. FMA1 f0, f28, f24, f0
  1453. FMA1 f2, f30, f24, f2
  1454. FMA2 f1, f28, f25, f1
  1455. FMA2 f3, f30, f25, f3
  1456. LFD f16, 24 * SIZE(AO)
  1457. LFD f17, 25 * SIZE(AO)
  1458. LFD f18, 26 * SIZE(AO)
  1459. LFD f19, 27 * SIZE(AO)
  1460. FMA1 f4, f28, f26, f4
  1461. FMA1 f6, f30, f26, f6
  1462. FMA2 f5, f28, f27, f5
  1463. FMA2 f7, f30, f27, f7
  1464. FMA4 f9, f29, f24, f9
  1465. FMA4 f11, f31, f24, f11
  1466. FMA3 f8, f29, f25, f8
  1467. FMA3 f10, f31, f25, f10
  1468. FMA4 f13, f29, f26, f13
  1469. FMA4 f15, f31, f26, f15
  1470. FMA3 f12, f29, f27, f12
  1471. FMA3 f14, f31, f27, f14
  1472. LFD f24, 28 * SIZE(BO)
  1473. LFD f25, 29 * SIZE(BO)
  1474. LFD f26, 30 * SIZE(BO)
  1475. LFD f27, 31 * SIZE(BO)
  1476. FMA1 f0, f16, f20, f0
  1477. FMA1 f2, f18, f20, f2
  1478. FMA2 f1, f16, f21, f1
  1479. FMA2 f3, f18, f21, f3
  1480. LFD f28, 28 * SIZE(AO)
  1481. LFD f29, 29 * SIZE(AO)
  1482. LFD f30, 30 * SIZE(AO)
  1483. LFD f31, 31 * SIZE(AO)
  1484. FMA1 f4, f16, f22, f4
  1485. FMA1 f6, f18, f22, f6
  1486. FMA2 f5, f16, f23, f5
  1487. FMA2 f7, f18, f23, f7
  1488. FMA4 f9, f17, f20, f9
  1489. FMA4 f11, f19, f20, f11
  1490. FMA3 f8, f17, f21, f8
  1491. FMA3 f10, f19, f21, f10
  1492. FMA4 f13, f17, f22, f13
  1493. FMA4 f15, f19, f22, f15
  1494. FMA3 f12, f17, f23, f12
  1495. FMA3 f14, f19, f23, f14
  1496. LFD f20, 32 * SIZE(BO)
  1497. LFD f21, 33 * SIZE(BO)
  1498. LFD f22, 34 * SIZE(BO)
  1499. LFD f23, 35 * SIZE(BO)
  1500. FMA1 f0, f28, f24, f0
  1501. FMA1 f2, f30, f24, f2
  1502. FMA2 f1, f28, f25, f1
  1503. FMA2 f3, f30, f25, f3
  1504. LFD f16, 32 * SIZE(AO)
  1505. LFD f17, 33 * SIZE(AO)
  1506. LFD f18, 34 * SIZE(AO)
  1507. LFD f19, 35 * SIZE(AO)
  1508. FMA1 f4, f28, f26, f4
  1509. FMA1 f6, f30, f26, f6
  1510. FMA2 f5, f28, f27, f5
  1511. FMA2 f7, f30, f27, f7
  1512. FMA4 f9, f29, f24, f9
  1513. FMA4 f11, f31, f24, f11
  1514. FMA3 f8, f29, f25, f8
  1515. FMA3 f10, f31, f25, f10
  1516. FMA4 f13, f29, f26, f13
  1517. FMA4 f15, f31, f26, f15
  1518. FMA3 f12, f29, f27, f12
  1519. FMA3 f14, f31, f27, f14
  1520. LFD f24, 36 * SIZE(BO)
  1521. LFD f25, 37 * SIZE(BO)
  1522. LFD f26, 38 * SIZE(BO)
  1523. LFD f27, 39 * SIZE(BO)
  1524. addi AO, AO, 32 * SIZE
  1525. addi BO, BO, 32 * SIZE
  1526. bdnz LL(32)
  1527. .align 4
  1528. LL(35):
  1529. lfd f30, ALPHA_R
  1530. lfd f31, ALPHA_I
  1531. dcbtst B, BB
  1532. addi BB, BB, 16 * SIZE
  1533. #ifndef TRMMKERNEL
  1534. andi. r0, K, 7
  1535. mtspr CTR, r0
  1536. ble LL(38)
  1537. #else
  1538. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1539. sub TEMP, K, KK
  1540. #elif defined(LEFT)
  1541. addi TEMP, KK, 2
  1542. #else
  1543. addi TEMP, KK, 2
  1544. #endif
  1545. andi. TEMP, TEMP, 7
  1546. mtspr CTR, TEMP
  1547. ble LL(38)
  1548. #endif
  1549. .align 4
  1550. LL(36):
  1551. FMA1 f0, f16, f20, f0
  1552. FMA1 f2, f18, f20, f2
  1553. FMA2 f1, f16, f21, f1
  1554. FMA2 f3, f18, f21, f3
  1555. FMA1 f4, f16, f22, f4
  1556. FMA1 f6, f18, f22, f6
  1557. FMA2 f5, f16, f23, f5
  1558. FMA2 f7, f18, f23, f7
  1559. FMA4 f9, f17, f20, f9
  1560. FMA4 f11, f19, f20, f11
  1561. FMA3 f8, f17, f21, f8
  1562. FMA3 f10, f19, f21, f10
  1563. LFD f16, 4 * SIZE(AO)
  1564. LFD f18, 6 * SIZE(AO)
  1565. LFD f20, 4 * SIZE(BO)
  1566. LFD f21, 5 * SIZE(BO)
  1567. FMA4 f13, f17, f22, f13
  1568. FMA4 f15, f19, f22, f15
  1569. FMA3 f12, f17, f23, f12
  1570. FMA3 f14, f19, f23, f14
  1571. LFD f17, 5 * SIZE(AO)
  1572. LFD f19, 7 * SIZE(AO)
  1573. LFD f22, 6 * SIZE(BO)
  1574. LFD f23, 7 * SIZE(BO)
  1575. addi AO, AO, 4 * SIZE
  1576. addi BO, BO, 4 * SIZE
  1577. bdnz LL(36)
  1578. .align 4
  1579. LL(38):
  1580. #ifndef TRMMKERNEL
  1581. LFD f16, 0 * SIZE(CO1)
  1582. LFD f17, 1 * SIZE(CO1)
  1583. LFD f18, 2 * SIZE(CO1)
  1584. LFD f19, 3 * SIZE(CO1)
  1585. FADD f0, f0, f8
  1586. FADD f1, f1, f9
  1587. FADD f2, f2, f10
  1588. FADD f3, f3, f11
  1589. LFD f20, 0 * SIZE(CO2)
  1590. LFD f21, 1 * SIZE(CO2)
  1591. LFD f22, 2 * SIZE(CO2)
  1592. LFD f23, 3 * SIZE(CO2)
  1593. FADD f4, f4, f12
  1594. FADD f5, f5, f13
  1595. FADD f6, f6, f14
  1596. FADD f7, f7, f15
  1597. FNMSUB f24, f31, f1, f16
  1598. FMADD f25, f31, f0, f17
  1599. FNMSUB f26, f31, f3, f18
  1600. FMADD f27, f31, f2, f19
  1601. FMADD f0, f30, f0, f24
  1602. FMADD f1, f30, f1, f25
  1603. FMADD f2, f30, f2, f26
  1604. FMADD f3, f30, f3, f27
  1605. FNMSUB f24, f31, f5, f20
  1606. FMADD f25, f31, f4, f21
  1607. FNMSUB f26, f31, f7, f22
  1608. FMADD f27, f31, f6, f23
  1609. FMADD f4, f30, f4, f24
  1610. FMADD f5, f30, f5, f25
  1611. FMADD f6, f30, f6, f26
  1612. FMADD f7, f30, f7, f27
  1613. #else
  1614. FADD f0, f0, f8
  1615. FADD f1, f1, f9
  1616. FADD f2, f2, f10
  1617. FADD f3, f3, f11
  1618. FADD f4, f4, f12
  1619. FADD f5, f5, f13
  1620. FADD f6, f6, f14
  1621. FADD f7, f7, f15
  1622. FMUL f16, f31, f1
  1623. FMUL f17, f31, f0
  1624. FMUL f18, f31, f3
  1625. FMUL f19, f31, f2
  1626. FMUL f20, f31, f5
  1627. FMUL f21, f31, f4
  1628. FMUL f22, f31, f7
  1629. FMUL f23, f31, f6
  1630. FMSUB f0, f30, f0, f16
  1631. FMADD f1, f30, f1, f17
  1632. FMADD f2, f30, f2, f18
  1633. FMADD f3, f30, f3, f19
  1634. FMSUB f4, f30, f4, f20
  1635. FMADD f5, f30, f5, f21
  1636. FMADD f6, f30, f6, f22
  1637. FMADD f7, f30, f7, f23
  1638. #endif
  1639. STFD f0, 0 * SIZE(CO1)
  1640. STFD f1, 1 * SIZE(CO1)
  1641. STFD f2, 2 * SIZE(CO1)
  1642. STFD f3, 3 * SIZE(CO1)
  1643. lfs f0, FZERO
  1644. fmr f1, f0
  1645. fmr f2, f0
  1646. fmr f3, f0
  1647. STFD f4, 0 * SIZE(CO2)
  1648. STFD f5, 1 * SIZE(CO2)
  1649. STFD f6, 2 * SIZE(CO2)
  1650. STFD f7, 3 * SIZE(CO2)
  1651. fmr f4, f0
  1652. fmr f5, f0
  1653. fmr f6, f0
  1654. fmr f7, f0
  1655. fmr f8, f0
  1656. fmr f9, f0
  1657. fmr f10, f0
  1658. fmr f11, f0
  1659. fmr f12, f0
  1660. fmr f13, f0
  1661. fmr f14, f0
  1662. fmr f15, f0
  1663. addi CO1, CO1, 4 * SIZE
  1664. addi CO2, CO2, 4 * SIZE
  1665. #ifdef TRMMKERNEL
  1666. #if ( defined(LEFT) && defined(TRANSA)) || \
  1667. (!defined(LEFT) && !defined(TRANSA))
  1668. sub TEMP, K, KK
  1669. #ifdef LEFT
  1670. addi TEMP, TEMP, -2
  1671. #else
  1672. addi TEMP, TEMP, -2
  1673. #endif
  1674. slwi r0, TEMP, 1 + ZBASE_SHIFT
  1675. slwi TEMP, TEMP, 1 + ZBASE_SHIFT
  1676. add AO, AO, r0
  1677. add BO, BO, TEMP
  1678. #endif
  1679. #ifdef LEFT
  1680. addi KK, KK, 2
  1681. #endif
  1682. #endif
  1683. addic. I, I, -1
  1684. bgt LL(31)
  1685. .align 4
  1686. LL(40):
  1687. andi. I, M, 1
  1688. ble LL(49)
  1689. #ifndef TRMMKERNEL
  1690. LFD f16, 0 * SIZE(AO)
  1691. LFD f17, 1 * SIZE(AO)
  1692. LFD f20, 0 * SIZE(B)
  1693. LFD f21, 1 * SIZE(B)
  1694. LFD f22, 2 * SIZE(B)
  1695. LFD f23, 3 * SIZE(B)
  1696. srawi. r0, K, 2
  1697. mr BO, B
  1698. mtspr CTR, r0
  1699. ble LL(45)
  1700. #else
  1701. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  1702. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  1703. LFD f16, 0 * SIZE(AO)
  1704. LFD f17, 1 * SIZE(AO)
  1705. LFD f20, 0 * SIZE(B)
  1706. LFD f21, 1 * SIZE(B)
  1707. LFD f22, 2 * SIZE(B)
  1708. LFD f23, 3 * SIZE(B)
  1709. mr BO, B
  1710. #else
  1711. slwi r0, KK, 0 + ZBASE_SHIFT
  1712. slwi TEMP, KK, 1 + ZBASE_SHIFT
  1713. add AO, AO, r0
  1714. add BO, B, TEMP
  1715. LFD f16, 0 * SIZE(AO)
  1716. LFD f17, 1 * SIZE(AO)
  1717. LFD f20, 0 * SIZE(BO)
  1718. LFD f21, 1 * SIZE(BO)
  1719. LFD f22, 2 * SIZE(BO)
  1720. LFD f23, 3 * SIZE(BO)
  1721. #endif
  1722. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1723. sub TEMP, K, KK
  1724. #elif defined(LEFT)
  1725. addi TEMP, KK, 1
  1726. #else
  1727. addi TEMP, KK, 2
  1728. #endif
  1729. srawi. TEMP, TEMP, 2
  1730. mtspr CTR, TEMP
  1731. ble LL(45)
  1732. #endif
  1733. .align 4
  1734. LL(42):
  1735. FMA1 f0, f16, f20, f0
  1736. FMA4 f3, f17, f20, f3
  1737. FMA2 f1, f16, f21, f1
  1738. FMA3 f2, f17, f21, f2
  1739. FMA1 f4, f16, f22, f4
  1740. FMA4 f7, f17, f22, f7
  1741. FMA2 f5, f16, f23, f5
  1742. FMA3 f6, f17, f23, f6
  1743. LFD f16, 2 * SIZE(AO)
  1744. LFD f17, 3 * SIZE(AO)
  1745. LFD f20, 4 * SIZE(BO)
  1746. LFD f21, 5 * SIZE(BO)
  1747. LFD f22, 6 * SIZE(BO)
  1748. LFD f23, 7 * SIZE(BO)
  1749. FMA1 f0, f16, f20, f0
  1750. FMA4 f3, f17, f20, f3
  1751. FMA2 f1, f16, f21, f1
  1752. FMA3 f2, f17, f21, f2
  1753. FMA1 f4, f16, f22, f4
  1754. FMA4 f7, f17, f22, f7
  1755. FMA2 f5, f16, f23, f5
  1756. FMA3 f6, f17, f23, f6
  1757. LFD f16, 4 * SIZE(AO)
  1758. LFD f17, 5 * SIZE(AO)
  1759. LFD f20, 8 * SIZE(BO)
  1760. LFD f21, 9 * SIZE(BO)
  1761. LFD f22, 10 * SIZE(BO)
  1762. LFD f23, 11 * SIZE(BO)
  1763. FMA1 f0, f16, f20, f0
  1764. FMA4 f3, f17, f20, f3
  1765. FMA2 f1, f16, f21, f1
  1766. FMA3 f2, f17, f21, f2
  1767. FMA1 f4, f16, f22, f4
  1768. FMA4 f7, f17, f22, f7
  1769. FMA2 f5, f16, f23, f5
  1770. FMA3 f6, f17, f23, f6
  1771. LFD f16, 6 * SIZE(AO)
  1772. LFD f17, 7 * SIZE(AO)
  1773. LFD f20, 12 * SIZE(BO)
  1774. LFD f21, 13 * SIZE(BO)
  1775. LFD f22, 14 * SIZE(BO)
  1776. LFD f23, 15 * SIZE(BO)
  1777. FMA1 f0, f16, f20, f0
  1778. FMA4 f3, f17, f20, f3
  1779. FMA2 f1, f16, f21, f1
  1780. FMA3 f2, f17, f21, f2
  1781. FMA1 f4, f16, f22, f4
  1782. FMA4 f7, f17, f22, f7
  1783. FMA2 f5, f16, f23, f5
  1784. FMA3 f6, f17, f23, f6
  1785. LFD f16, 8 * SIZE(AO)
  1786. LFD f17, 9 * SIZE(AO)
  1787. LFD f20, 16 * SIZE(BO)
  1788. LFD f21, 17 * SIZE(BO)
  1789. LFD f22, 18 * SIZE(BO)
  1790. LFD f23, 19 * SIZE(BO)
  1791. addi AO, AO, 8 * SIZE
  1792. addi BO, BO, 16 * SIZE
  1793. bdnz LL(42)
  1794. .align 4
  1795. LL(45):
  1796. lfd f30, ALPHA_R
  1797. lfd f31, ALPHA_I
  1798. #ifndef TRMMKERNEL
  1799. andi. r0, K, 3
  1800. mtspr CTR, r0
  1801. ble LL(48)
  1802. #else
  1803. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1804. sub TEMP, K, KK
  1805. #elif defined(LEFT)
  1806. addi TEMP, KK, 1
  1807. #else
  1808. addi TEMP, KK, 2
  1809. #endif
  1810. andi. TEMP, TEMP, 3
  1811. mtspr CTR, TEMP
  1812. ble LL(48)
  1813. #endif
  1814. .align 4
  1815. LL(46):
  1816. FMA1 f0, f16, f20, f0
  1817. FMA4 f3, f17, f20, f3
  1818. FMA2 f1, f16, f21, f1
  1819. FMA3 f2, f17, f21, f2
  1820. FMA1 f4, f16, f22, f4
  1821. FMA4 f7, f17, f22, f7
  1822. FMA2 f5, f16, f23, f5
  1823. FMA3 f6, f17, f23, f6
  1824. LFD f16, 2 * SIZE(AO)
  1825. LFD f17, 3 * SIZE(AO)
  1826. LFD f20, 4 * SIZE(BO)
  1827. LFD f21, 5 * SIZE(BO)
  1828. LFD f22, 6 * SIZE(BO)
  1829. LFD f23, 7 * SIZE(BO)
  1830. addi AO, AO, 2 * SIZE
  1831. addi BO, BO, 4 * SIZE
  1832. bdnz LL(46)
  1833. .align 4
  1834. LL(48):
  1835. #ifndef TRMMKERNEL
  1836. LFD f16, 0 * SIZE(CO1)
  1837. LFD f17, 1 * SIZE(CO1)
  1838. LFD f20, 0 * SIZE(CO2)
  1839. LFD f21, 1 * SIZE(CO2)
  1840. FADD f0, f0, f2
  1841. FADD f1, f1, f3
  1842. FADD f4, f4, f6
  1843. FADD f5, f5, f7
  1844. FNMSUB f24, f31, f1, f16
  1845. FMADD f25, f31, f0, f17
  1846. FNMSUB f26, f31, f5, f20
  1847. FMADD f27, f31, f4, f21
  1848. FMADD f0, f30, f0, f24
  1849. FMADD f1, f30, f1, f25
  1850. FMADD f4, f30, f4, f26
  1851. FMADD f5, f30, f5, f27
  1852. #else
  1853. FADD f0, f0, f2
  1854. FADD f1, f1, f3
  1855. FADD f4, f4, f6
  1856. FADD f5, f5, f7
  1857. FMUL f16, f31, f1
  1858. FMUL f17, f31, f0
  1859. FMUL f18, f31, f5
  1860. FMUL f19, f31, f4
  1861. FMSUB f0, f30, f0, f16
  1862. FMADD f1, f30, f1, f17
  1863. FMSUB f4, f30, f4, f18
  1864. FMADD f5, f30, f5, f19
  1865. #endif
  1866. STFD f0, 0 * SIZE(CO1)
  1867. STFD f1, 1 * SIZE(CO1)
  1868. STFD f4, 0 * SIZE(CO2)
  1869. STFD f5, 1 * SIZE(CO2)
  1870. addi CO1, CO1, 2 * SIZE
  1871. addi CO2, CO2, 2 * SIZE
  1872. #ifdef TRMMKERNEL
  1873. #if ( defined(LEFT) && defined(TRANSA)) || \
  1874. (!defined(LEFT) && !defined(TRANSA))
  1875. sub TEMP, K, KK
  1876. #ifdef LEFT
  1877. addi TEMP, TEMP, -1
  1878. #else
  1879. addi TEMP, TEMP, -2
  1880. #endif
  1881. slwi r0, TEMP, 0 + ZBASE_SHIFT
  1882. slwi TEMP, TEMP, 1 + ZBASE_SHIFT
  1883. add AO, AO, r0
  1884. add BO, BO, TEMP
  1885. #endif
  1886. #ifdef LEFT
  1887. addi KK, KK, 1
  1888. #endif
  1889. #endif
  1890. .align 4
  1891. LL(49):
  1892. #if defined(TRMMKERNEL) && !defined(LEFT)
  1893. addi KK, KK, 2
  1894. #endif
  1895. mr B, BO
  1896. .align 4
  1897. LL(50):
  1898. andi. J, N, 1
  1899. ble LL(999)
  1900. mr CO1, C
  1901. add C, CO1, LDC
  1902. #if defined(TRMMKERNEL) && defined(LEFT)
  1903. mr KK, OFFSET
  1904. #endif
  1905. mr AO, A
  1906. lfs f0, FZERO
  1907. fmr f1, f0
  1908. fmr f2, f0
  1909. fmr f3, f0
  1910. fmr f8, f0
  1911. fmr f9, f0
  1912. fmr f10, f0
  1913. fmr f11, f0
  1914. srawi. I, M, 1
  1915. ble LL(60)
  1916. .align 4
  1917. LL(51):
  1918. #ifndef TRMMKERNEL
  1919. LFD f16, 0 * SIZE(AO)
  1920. LFD f17, 1 * SIZE(AO)
  1921. LFD f18, 2 * SIZE(AO)
  1922. LFD f19, 3 * SIZE(AO)
  1923. LFD f20, 0 * SIZE(B)
  1924. LFD f21, 1 * SIZE(B)
  1925. LFD f22, 2 * SIZE(B)
  1926. LFD f23, 3 * SIZE(B)
  1927. dcbtst CO1, PREC
  1928. srawi. r0, K, 3
  1929. mr BO, B
  1930. mtspr CTR, r0
  1931. ble LL(55)
  1932. #else
  1933. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  1934. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  1935. LFD f16, 0 * SIZE(AO)
  1936. LFD f17, 1 * SIZE(AO)
  1937. LFD f18, 2 * SIZE(AO)
  1938. LFD f19, 3 * SIZE(AO)
  1939. LFD f20, 0 * SIZE(B)
  1940. LFD f21, 1 * SIZE(B)
  1941. LFD f22, 2 * SIZE(B)
  1942. LFD f23, 3 * SIZE(B)
  1943. mr BO, B
  1944. #else
  1945. slwi r0, KK, 1 + ZBASE_SHIFT
  1946. slwi TEMP, KK, 0 + ZBASE_SHIFT
  1947. add AO, AO, r0
  1948. add BO, B, TEMP
  1949. LFD f16, 0 * SIZE(AO)
  1950. LFD f17, 1 * SIZE(AO)
  1951. LFD f18, 2 * SIZE(AO)
  1952. LFD f19, 3 * SIZE(AO)
  1953. LFD f20, 0 * SIZE(BO)
  1954. LFD f21, 1 * SIZE(BO)
  1955. LFD f22, 2 * SIZE(BO)
  1956. LFD f23, 3 * SIZE(BO)
  1957. #endif
  1958. dcbtst CO1, PREC
  1959. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  1960. sub TEMP, K, KK
  1961. #elif defined(LEFT)
  1962. addi TEMP, KK, 2
  1963. #else
  1964. addi TEMP, KK, 1
  1965. #endif
  1966. srawi. TEMP, TEMP, 3
  1967. mtspr CTR, TEMP
  1968. ble LL(55)
  1969. #endif
  1970. .align 4
  1971. LL(52):
  1972. dcbt AO, PREA
  1973. dcbtst BO, PREA
  1974. FMA1 f0, f16, f20, f0
  1975. FMA1 f2, f18, f20, f2
  1976. FMA2 f1, f16, f21, f1
  1977. FMA2 f3, f18, f21, f3
  1978. FMA4 f9, f17, f20, f9
  1979. FMA4 f11, f19, f20, f11
  1980. FMA3 f8, f17, f21, f8
  1981. FMA3 f10, f19, f21, f10
  1982. LFD f16, 4 * SIZE(AO)
  1983. LFD f17, 5 * SIZE(AO)
  1984. LFD f18, 6 * SIZE(AO)
  1985. LFD f19, 7 * SIZE(AO)
  1986. FMA1 f0, f16, f22, f0
  1987. FMA1 f2, f18, f22, f2
  1988. FMA2 f1, f16, f23, f1
  1989. FMA2 f3, f18, f23, f3
  1990. FMA4 f9, f17, f22, f9
  1991. FMA4 f11, f19, f22, f11
  1992. FMA3 f8, f17, f23, f8
  1993. FMA3 f10, f19, f23, f10
  1994. LFD f16, 8 * SIZE(AO)
  1995. LFD f17, 9 * SIZE(AO)
  1996. LFD f18, 10 * SIZE(AO)
  1997. LFD f19, 11 * SIZE(AO)
  1998. LFD f20, 4 * SIZE(BO)
  1999. LFD f21, 5 * SIZE(BO)
  2000. LFD f22, 6 * SIZE(BO)
  2001. LFD f23, 7 * SIZE(BO)
  2002. FMA1 f0, f16, f20, f0
  2003. FMA1 f2, f18, f20, f2
  2004. FMA2 f1, f16, f21, f1
  2005. FMA2 f3, f18, f21, f3
  2006. FMA4 f9, f17, f20, f9
  2007. FMA4 f11, f19, f20, f11
  2008. FMA3 f8, f17, f21, f8
  2009. FMA3 f10, f19, f21, f10
  2010. LFD f16, 12 * SIZE(AO)
  2011. LFD f17, 13 * SIZE(AO)
  2012. LFD f18, 14 * SIZE(AO)
  2013. LFD f19, 15 * SIZE(AO)
  2014. FMA1 f0, f16, f22, f0
  2015. FMA1 f2, f18, f22, f2
  2016. FMA2 f1, f16, f23, f1
  2017. FMA2 f3, f18, f23, f3
  2018. FMA4 f9, f17, f22, f9
  2019. FMA4 f11, f19, f22, f11
  2020. FMA3 f8, f17, f23, f8
  2021. FMA3 f10, f19, f23, f10
  2022. LFD f16, 16 * SIZE(AO)
  2023. LFD f17, 17 * SIZE(AO)
  2024. LFD f18, 18 * SIZE(AO)
  2025. LFD f19, 19 * SIZE(AO)
  2026. LFD f20, 8 * SIZE(BO)
  2027. LFD f21, 9 * SIZE(BO)
  2028. LFD f22, 10 * SIZE(BO)
  2029. LFD f23, 11 * SIZE(BO)
  2030. FMA1 f0, f16, f20, f0
  2031. FMA1 f2, f18, f20, f2
  2032. FMA2 f1, f16, f21, f1
  2033. FMA2 f3, f18, f21, f3
  2034. FMA4 f9, f17, f20, f9
  2035. FMA4 f11, f19, f20, f11
  2036. FMA3 f8, f17, f21, f8
  2037. FMA3 f10, f19, f21, f10
  2038. LFD f16, 20 * SIZE(AO)
  2039. LFD f17, 21 * SIZE(AO)
  2040. LFD f18, 22 * SIZE(AO)
  2041. LFD f19, 23 * SIZE(AO)
  2042. FMA1 f0, f16, f22, f0
  2043. FMA1 f2, f18, f22, f2
  2044. FMA2 f1, f16, f23, f1
  2045. FMA2 f3, f18, f23, f3
  2046. FMA4 f9, f17, f22, f9
  2047. FMA4 f11, f19, f22, f11
  2048. FMA3 f8, f17, f23, f8
  2049. FMA3 f10, f19, f23, f10
  2050. LFD f16, 24 * SIZE(AO)
  2051. LFD f17, 25 * SIZE(AO)
  2052. LFD f18, 26 * SIZE(AO)
  2053. LFD f19, 27 * SIZE(AO)
  2054. LFD f20, 12 * SIZE(BO)
  2055. LFD f21, 13 * SIZE(BO)
  2056. LFD f22, 14 * SIZE(BO)
  2057. LFD f23, 15 * SIZE(BO)
  2058. FMA1 f0, f16, f20, f0
  2059. FMA1 f2, f18, f20, f2
  2060. FMA2 f1, f16, f21, f1
  2061. FMA2 f3, f18, f21, f3
  2062. FMA4 f9, f17, f20, f9
  2063. FMA4 f11, f19, f20, f11
  2064. FMA3 f8, f17, f21, f8
  2065. FMA3 f10, f19, f21, f10
  2066. LFD f16, 28 * SIZE(AO)
  2067. LFD f17, 29 * SIZE(AO)
  2068. LFD f18, 30 * SIZE(AO)
  2069. LFD f19, 31 * SIZE(AO)
  2070. FMA1 f0, f16, f22, f0
  2071. FMA1 f2, f18, f22, f2
  2072. FMA2 f1, f16, f23, f1
  2073. FMA2 f3, f18, f23, f3
  2074. FMA4 f9, f17, f22, f9
  2075. FMA4 f11, f19, f22, f11
  2076. FMA3 f8, f17, f23, f8
  2077. FMA3 f10, f19, f23, f10
  2078. LFD f16, 32 * SIZE(AO)
  2079. LFD f17, 33 * SIZE(AO)
  2080. LFD f18, 34 * SIZE(AO)
  2081. LFD f19, 35 * SIZE(AO)
  2082. LFD f20, 16 * SIZE(BO)
  2083. LFD f21, 17 * SIZE(BO)
  2084. LFD f22, 18 * SIZE(BO)
  2085. LFD f23, 19 * SIZE(BO)
  2086. addi AO, AO, 32 * SIZE
  2087. addi BO, BO, 16 * SIZE
  2088. bdnz LL(52)
  2089. .align 4
  2090. LL(55):
  2091. lfd f30, ALPHA_R
  2092. lfd f31, ALPHA_I
  2093. #ifndef TRMMKERNEL
  2094. andi. r0, K, 7
  2095. mtspr CTR, r0
  2096. ble LL(58)
  2097. #else
  2098. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  2099. sub TEMP, K, KK
  2100. #elif defined(LEFT)
  2101. addi TEMP, KK, 2
  2102. #else
  2103. addi TEMP, KK, 1
  2104. #endif
  2105. andi. TEMP, TEMP, 7
  2106. mtspr CTR, TEMP
  2107. ble LL(58)
  2108. #endif
  2109. .align 4
  2110. LL(56):
  2111. FMA1 f0, f16, f20, f0
  2112. FMA1 f2, f18, f20, f2
  2113. FMA2 f1, f16, f21, f1
  2114. FMA2 f3, f18, f21, f3
  2115. LFD f16, 4 * SIZE(AO)
  2116. LFD f18, 6 * SIZE(AO)
  2117. FMA4 f9, f17, f20, f9
  2118. FMA4 f11, f19, f20, f11
  2119. FMA3 f8, f17, f21, f8
  2120. FMA3 f10, f19, f21, f10
  2121. LFD f17, 5 * SIZE(AO)
  2122. LFD f19, 7 * SIZE(AO)
  2123. LFD f20, 2 * SIZE(BO)
  2124. LFD f21, 3 * SIZE(BO)
  2125. addi AO, AO, 4 * SIZE
  2126. addi BO, BO, 2 * SIZE
  2127. bdnz LL(56)
  2128. .align 4
  2129. LL(58):
  2130. #ifndef TRMMKERNEL
  2131. LFD f16, 0 * SIZE(CO1)
  2132. LFD f17, 1 * SIZE(CO1)
  2133. LFD f18, 2 * SIZE(CO1)
  2134. LFD f19, 3 * SIZE(CO1)
  2135. FADD f0, f0, f8
  2136. FADD f1, f1, f9
  2137. FADD f2, f2, f10
  2138. FADD f3, f3, f11
  2139. FNMSUB f24, f31, f1, f16
  2140. FMADD f25, f31, f0, f17
  2141. FNMSUB f26, f31, f3, f18
  2142. FMADD f27, f31, f2, f19
  2143. FMADD f0, f30, f0, f24
  2144. FMADD f1, f30, f1, f25
  2145. FMADD f2, f30, f2, f26
  2146. FMADD f3, f30, f3, f27
  2147. #else
  2148. FADD f0, f0, f8
  2149. FADD f1, f1, f9
  2150. FADD f2, f2, f10
  2151. FADD f3, f3, f11
  2152. FMUL f16, f31, f1
  2153. FMUL f17, f31, f0
  2154. FMUL f18, f31, f3
  2155. FMUL f19, f31, f2
  2156. FMSUB f0, f30, f0, f16
  2157. FMADD f1, f30, f1, f17
  2158. FMADD f2, f30, f2, f18
  2159. FMADD f3, f30, f3, f19
  2160. #endif
  2161. STFD f0, 0 * SIZE(CO1)
  2162. STFD f1, 1 * SIZE(CO1)
  2163. STFD f2, 2 * SIZE(CO1)
  2164. STFD f3, 3 * SIZE(CO1)
  2165. lfs f0, FZERO
  2166. fmr f1, f0
  2167. fmr f2, f0
  2168. fmr f3, f0
  2169. fmr f8, f0
  2170. fmr f9, f0
  2171. fmr f10, f0
  2172. fmr f11, f0
  2173. addi CO1, CO1, 4 * SIZE
  2174. #ifdef TRMMKERNEL
  2175. #if ( defined(LEFT) && defined(TRANSA)) || \
  2176. (!defined(LEFT) && !defined(TRANSA))
  2177. sub TEMP, K, KK
  2178. #ifdef LEFT
  2179. addi TEMP, TEMP, -2
  2180. #else
  2181. addi TEMP, TEMP, -1
  2182. #endif
  2183. slwi r0, TEMP, 1 + ZBASE_SHIFT
  2184. slwi TEMP, TEMP, 0 + ZBASE_SHIFT
  2185. add AO, AO, r0
  2186. add BO, BO, TEMP
  2187. #endif
  2188. #ifdef LEFT
  2189. addi KK, KK, 2
  2190. #endif
  2191. #endif
  2192. addic. I, I, -1
  2193. bgt LL(51)
  2194. .align 4
  2195. LL(60):
  2196. andi. I, M, 1
  2197. ble LL(999)
  2198. #ifndef TRMMKERNEL
  2199. LFD f16, 0 * SIZE(AO)
  2200. LFD f17, 1 * SIZE(AO)
  2201. LFD f18, 2 * SIZE(AO)
  2202. LFD f19, 3 * SIZE(AO)
  2203. LFD f20, 0 * SIZE(B)
  2204. LFD f21, 1 * SIZE(B)
  2205. LFD f22, 2 * SIZE(B)
  2206. LFD f23, 3 * SIZE(B)
  2207. srawi. r0, K, 2
  2208. mr BO, B
  2209. mtspr CTR, r0
  2210. ble LL(65)
  2211. #else
  2212. #if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \
  2213. (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA))
  2214. LFD f16, 0 * SIZE(AO)
  2215. LFD f17, 1 * SIZE(AO)
  2216. LFD f18, 2 * SIZE(AO)
  2217. LFD f19, 3 * SIZE(AO)
  2218. LFD f20, 0 * SIZE(B)
  2219. LFD f21, 1 * SIZE(B)
  2220. LFD f22, 2 * SIZE(B)
  2221. LFD f23, 3 * SIZE(B)
  2222. mr BO, B
  2223. #else
  2224. slwi r0, KK, 0 + ZBASE_SHIFT
  2225. slwi TEMP, KK, 0 + ZBASE_SHIFT
  2226. add AO, AO, r0
  2227. add BO, B, TEMP
  2228. LFD f16, 0 * SIZE(AO)
  2229. LFD f17, 1 * SIZE(AO)
  2230. LFD f18, 2 * SIZE(AO)
  2231. LFD f19, 3 * SIZE(AO)
  2232. LFD f20, 0 * SIZE(BO)
  2233. LFD f21, 1 * SIZE(BO)
  2234. LFD f22, 2 * SIZE(BO)
  2235. LFD f23, 3 * SIZE(BO)
  2236. #endif
  2237. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  2238. sub TEMP, K, KK
  2239. #elif defined(LEFT)
  2240. addi TEMP, KK, 1
  2241. #else
  2242. addi TEMP, KK, 1
  2243. #endif
  2244. srawi. TEMP, TEMP, 2
  2245. mtspr CTR, TEMP
  2246. ble LL(65)
  2247. #endif
  2248. .align 4
  2249. LL(62):
  2250. FMA1 f0, f16, f20, f0
  2251. FMA4 f3, f17, f20, f3
  2252. FMA2 f1, f16, f21, f1
  2253. FMA3 f2, f17, f21, f2
  2254. LFD f16, 4 * SIZE(AO)
  2255. LFD f17, 5 * SIZE(AO)
  2256. LFD f20, 4 * SIZE(BO)
  2257. LFD f21, 5 * SIZE(BO)
  2258. FMA1 f0, f18, f22, f0
  2259. FMA4 f3, f19, f22, f3
  2260. FMA2 f1, f18, f23, f1
  2261. FMA3 f2, f19, f23, f2
  2262. LFD f18, 6 * SIZE(AO)
  2263. LFD f19, 7 * SIZE(AO)
  2264. LFD f22, 6 * SIZE(BO)
  2265. LFD f23, 7 * SIZE(BO)
  2266. FMA1 f0, f16, f20, f0
  2267. FMA4 f3, f17, f20, f3
  2268. FMA2 f1, f16, f21, f1
  2269. FMA3 f2, f17, f21, f2
  2270. LFD f16, 8 * SIZE(AO)
  2271. LFD f17, 9 * SIZE(AO)
  2272. LFD f20, 8 * SIZE(BO)
  2273. LFD f21, 9 * SIZE(BO)
  2274. FMA1 f0, f18, f22, f0
  2275. FMA4 f3, f19, f22, f3
  2276. FMA2 f1, f18, f23, f1
  2277. FMA3 f2, f19, f23, f2
  2278. LFD f18, 10 * SIZE(AO)
  2279. LFD f19, 11 * SIZE(AO)
  2280. LFD f22, 10 * SIZE(BO)
  2281. LFD f23, 11 * SIZE(BO)
  2282. addi AO, AO, 8 * SIZE
  2283. addi BO, BO, 8 * SIZE
  2284. bdnz LL(62)
  2285. .align 4
  2286. LL(65):
  2287. lfd f30, ALPHA_R
  2288. lfd f31, ALPHA_I
  2289. #ifndef TRMMKERNEL
  2290. andi. r0, K, 3
  2291. mtspr CTR, r0
  2292. ble LL(68)
  2293. #else
  2294. #if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
  2295. sub TEMP, K, KK
  2296. #elif defined(LEFT)
  2297. addi TEMP, KK, 1
  2298. #else
  2299. addi TEMP, KK, 1
  2300. #endif
  2301. andi. TEMP, TEMP, 3
  2302. mtspr CTR, TEMP
  2303. ble LL(68)
  2304. #endif
  2305. .align 4
  2306. LL(66):
  2307. FMA1 f0, f16, f20, f0
  2308. FMA4 f3, f17, f20, f3
  2309. LFD f20, 2 * SIZE(BO)
  2310. FMA2 f1, f16, f21, f1
  2311. LFD f16, 2 * SIZE(AO)
  2312. FMA3 f2, f17, f21, f2
  2313. LFD f17, 3 * SIZE(AO)
  2314. LFD f21, 3 * SIZE(BO)
  2315. addi AO, AO, 2 * SIZE
  2316. addi BO, BO, 2 * SIZE
  2317. bdnz LL(66)
  2318. .align 4
  2319. LL(68):
  2320. #ifndef TRMMKERNEL
  2321. LFD f16, 0 * SIZE(CO1)
  2322. LFD f17, 1 * SIZE(CO1)
  2323. FADD f0, f0, f2
  2324. FADD f1, f1, f3
  2325. FNMSUB f24, f31, f1, f16
  2326. FMADD f25, f31, f0, f17
  2327. FMADD f0, f30, f0, f24
  2328. FMADD f1, f30, f1, f25
  2329. #else
  2330. FADD f0, f0, f2
  2331. FADD f1, f1, f3
  2332. FMUL f16, f31, f1
  2333. FMUL f17, f31, f0
  2334. FMSUB f0, f30, f0, f16
  2335. FMADD f1, f30, f1, f17
  2336. #endif
  2337. STFD f0, 0 * SIZE(CO1)
  2338. STFD f1, 1 * SIZE(CO1)
  2339. addi CO1, CO1, 2 * SIZE
  2340. #ifdef TRMMKERNEL
  2341. #if ( defined(LEFT) && defined(TRANSA)) || \
  2342. (!defined(LEFT) && !defined(TRANSA))
  2343. sub TEMP, K, KK
  2344. #ifdef LEFT
  2345. addi TEMP, TEMP, -1
  2346. #else
  2347. addi TEMP, TEMP, -1
  2348. #endif
  2349. slwi r0, TEMP, 0 + ZBASE_SHIFT
  2350. slwi TEMP, TEMP, 0 + ZBASE_SHIFT
  2351. add AO, AO, r0
  2352. add BO, BO, TEMP
  2353. #endif
  2354. #ifdef LEFT
  2355. addi KK, KK, 1
  2356. #endif
  2357. #endif
  2358. .align 4
  2359. LL(999):
  2360. addi r3, 0, 0
  2361. lfd f14, 0(SP)
  2362. lfd f15, 8(SP)
  2363. lfd f16, 16(SP)
  2364. lfd f17, 24(SP)
  2365. lfd f18, 32(SP)
  2366. lfd f19, 40(SP)
  2367. lfd f20, 48(SP)
  2368. lfd f21, 56(SP)
  2369. lfd f22, 64(SP)
  2370. lfd f23, 72(SP)
  2371. lfd f24, 80(SP)
  2372. lfd f25, 88(SP)
  2373. lfd f26, 96(SP)
  2374. lfd f27, 104(SP)
  2375. lfd f28, 112(SP)
  2376. lfd f29, 120(SP)
  2377. lfd f30, 128(SP)
  2378. lfd f31, 136(SP)
  2379. #ifdef __64BIT__
  2380. ld r31, 144(SP)
  2381. ld r30, 152(SP)
  2382. ld r29, 160(SP)
  2383. ld r28, 168(SP)
  2384. ld r27, 176(SP)
  2385. ld r26, 184(SP)
  2386. ld r25, 192(SP)
  2387. ld r24, 200(SP)
  2388. ld r23, 208(SP)
  2389. ld r22, 216(SP)
  2390. ld r21, 224(SP)
  2391. #ifdef TRMMKERNEL
  2392. ld r20, 232(SP)
  2393. ld r19, 240(SP)
  2394. #endif
  2395. #else
  2396. lwz r31, 144(SP)
  2397. lwz r30, 148(SP)
  2398. lwz r29, 152(SP)
  2399. lwz r28, 156(SP)
  2400. lwz r27, 160(SP)
  2401. lwz r26, 164(SP)
  2402. lwz r25, 168(SP)
  2403. lwz r24, 172(SP)
  2404. lwz r23, 176(SP)
  2405. lwz r22, 180(SP)
  2406. lwz r21, 184(SP)
  2407. #ifdef TRMMKERNEL
  2408. lwz r20, 188(SP)
  2409. lwz r19, 192(SP)
  2410. #endif
  2411. #endif
  2412. addi SP, SP, STACKSIZE
  2413. blr
  2414. EPILOGUE
  2415. #endif