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sum.S 8.4 kB

rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
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  1. /*********************************************************************/
  2. /* Copyright 2009, 2010 The University of Texas at Austin. */
  3. /* All rights reserved. */
  4. /* */
  5. /* Redistribution and use in source and binary forms, with or */
  6. /* without modification, are permitted provided that the following */
  7. /* conditions are met: */
  8. /* */
  9. /* 1. Redistributions of source code must retain the above */
  10. /* copyright notice, this list of conditions and the following */
  11. /* disclaimer. */
  12. /* */
  13. /* 2. Redistributions in binary form must reproduce the above */
  14. /* copyright notice, this list of conditions and the following */
  15. /* disclaimer in the documentation and/or other materials */
  16. /* provided with the distribution. */
  17. /* */
  18. /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
  19. /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
  20. /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
  21. /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
  22. /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
  23. /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
  24. /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
  25. /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
  26. /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
  27. /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
  28. /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
  29. /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
  30. /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
  31. /* POSSIBILITY OF SUCH DAMAGE. */
  32. /* */
  33. /* The views and conclusions contained in the software and */
  34. /* documentation are those of the authors and should not be */
  35. /* interpreted as representing official policies, either expressed */
  36. /* or implied, of The University of Texas at Austin. */
  37. /*********************************************************************/
  38. #define ASSEMBLER
  39. #include "common.h"
  40. #define N r3
  41. #define X r4
  42. #define INCX r5
  43. #define PREA r8
  44. #define FZERO f0
  45. #define STACKSIZE 160
  46. PROLOGUE
  47. PROFCODE
  48. addi SP, SP, -STACKSIZE
  49. li r0, 0
  50. stfd f14, 0(SP)
  51. stfd f15, 8(SP)
  52. stfd f16, 16(SP)
  53. stfd f17, 24(SP)
  54. stfd f18, 32(SP)
  55. stfd f19, 40(SP)
  56. stfd f20, 48(SP)
  57. stfd f21, 56(SP)
  58. stfd f22, 64(SP)
  59. stfd f23, 72(SP)
  60. stfd f24, 80(SP)
  61. stfd f25, 88(SP)
  62. stfd f26, 96(SP)
  63. stfd f27, 104(SP)
  64. stfd f28, 112(SP)
  65. stfd f29, 120(SP)
  66. stfd f30, 128(SP)
  67. stfd f31, 136(SP)
  68. stw r0, 144(SP)
  69. lfs FZERO,144(SP)
  70. #ifdef F_INTERFACE
  71. LDINT N, 0(N)
  72. LDINT INCX, 0(INCX)
  73. #endif
  74. slwi INCX, INCX, BASE_SHIFT
  75. fmr f1, FZERO
  76. fmr f2, FZERO
  77. fmr f3, FZERO
  78. fmr f4, FZERO
  79. fmr f5, FZERO
  80. fmr f6, FZERO
  81. fmr f7, FZERO
  82. li PREA, L1_PREFETCHSIZE
  83. cmpwi cr0, N, 0
  84. ble- LL(999)
  85. cmpwi cr0, INCX, 0
  86. ble- LL(999)
  87. cmpwi cr0, INCX, SIZE
  88. bne- cr0, LL(100)
  89. srawi. r0, N, 4
  90. mtspr CTR, r0
  91. beq- cr0, LL(50)
  92. .align 4
  93. LFD f8, 0 * SIZE(X)
  94. LFD f9, 1 * SIZE(X)
  95. LFD f10, 2 * SIZE(X)
  96. LFD f11, 3 * SIZE(X)
  97. LFD f12, 4 * SIZE(X)
  98. LFD f13, 5 * SIZE(X)
  99. LFD f14, 6 * SIZE(X)
  100. LFD f15, 7 * SIZE(X)
  101. LFD f24, 8 * SIZE(X)
  102. LFD f25, 9 * SIZE(X)
  103. LFD f26, 10 * SIZE(X)
  104. LFD f27, 11 * SIZE(X)
  105. LFD f28, 12 * SIZE(X)
  106. LFD f29, 13 * SIZE(X)
  107. LFD f30, 14 * SIZE(X)
  108. LFD f31, 15 * SIZE(X)
  109. fmr f16, f8
  110. fmr f17, f9
  111. fmr f18, f10
  112. fmr f19, f11
  113. fmr f20, f12
  114. fmr f21, f13
  115. fmr f22, f14
  116. fmr f23, f15
  117. bdz LL(20)
  118. .align 4
  119. LL(10):
  120. FADD f0, f0, f16
  121. fmr f16, f24
  122. FADD f1, f1, f17
  123. fmr f17, f25
  124. FADD f2, f2, f18
  125. fmr f18, f26
  126. FADD f3, f3, f19
  127. fmr f19, f27
  128. LFD f8, 16 * SIZE(X)
  129. LFD f9, 17 * SIZE(X)
  130. LFD f10, 18 * SIZE(X)
  131. LFD f11, 19 * SIZE(X)
  132. FADD f4, f4, f20
  133. fmr f20, f28
  134. FADD f5, f5, f21
  135. fmr f21, f29
  136. FADD f6, f6, f22
  137. fmr f22, f30
  138. FADD f7, f7, f23
  139. fmr f23, f31
  140. LFD f12, 20 * SIZE(X)
  141. LFD f13, 21 * SIZE(X)
  142. LFD f14, 22 * SIZE(X)
  143. LFD f15, 23 * SIZE(X)
  144. FADD f0, f0, f16
  145. fmr f16, f8
  146. FADD f1, f1, f17
  147. fmr f17, f9
  148. FADD f2, f2, f18
  149. fmr f18, f10
  150. FADD f3, f3, f19
  151. fmr f19, f11
  152. LFD f24, 24 * SIZE(X)
  153. LFD f25, 25 * SIZE(X)
  154. LFD f26, 26 * SIZE(X)
  155. LFD f27, 27 * SIZE(X)
  156. FADD f4, f4, f20
  157. fmr f20, f12
  158. FADD f5, f5, f21
  159. fmr f21, f13
  160. FADD f6, f6, f22
  161. fmr f22, f14
  162. FADD f7, f7, f23
  163. fmr f23, f15
  164. LFD f28, 28 * SIZE(X)
  165. LFD f29, 29 * SIZE(X)
  166. LFD f30, 30 * SIZE(X)
  167. LFD f31, 31 * SIZE(X)
  168. #ifndef POWER6
  169. L1_PREFETCH X, PREA
  170. #endif
  171. addi X, X, 16 * SIZE
  172. #ifdef POWER6
  173. L1_PREFETCH X, PREA
  174. #endif
  175. bdnz LL(10)
  176. .align 4
  177. LL(20):
  178. FADD f0, f0, f16
  179. fmr f16, f24
  180. FADD f1, f1, f17
  181. fmr f17, f25
  182. FADD f2, f2, f18
  183. fmr f18, f26
  184. FADD f3, f3, f19
  185. fmr f19, f27
  186. FADD f4, f4, f20
  187. fmr f20, f28
  188. FADD f5, f5, f21
  189. fmr f21, f29
  190. FADD f6, f6, f22
  191. fmr f22, f30
  192. FADD f7, f7, f23
  193. fmr f23, f31
  194. FADD f0, f0, f16
  195. FADD f1, f1, f17
  196. FADD f2, f2, f18
  197. FADD f3, f3, f19
  198. FADD f4, f4, f20
  199. FADD f5, f5, f21
  200. FADD f6, f6, f22
  201. FADD f7, f7, f23
  202. addi X, X, 16 * SIZE
  203. .align 4
  204. LL(50):
  205. andi. r0, N, 15
  206. mtspr CTR, r0
  207. beq LL(999)
  208. .align 4
  209. LL(60):
  210. LFD f8, 0 * SIZE(X)
  211. addi X, X, 1 * SIZE
  212. FADD f0, f0, f8
  213. bdnz LL(60)
  214. b LL(999)
  215. .align 4
  216. LL(100):
  217. sub X, X, INCX
  218. srawi. r0, N, 4
  219. mtspr CTR, r0
  220. beq- LL(150)
  221. LFDUX f8, X, INCX
  222. LFDUX f9, X, INCX
  223. LFDUX f10, X, INCX
  224. LFDUX f11, X, INCX
  225. LFDUX f12, X, INCX
  226. LFDUX f13, X, INCX
  227. LFDUX f14, X, INCX
  228. LFDUX f15, X, INCX
  229. LFDUX f24, X, INCX
  230. LFDUX f25, X, INCX
  231. LFDUX f26, X, INCX
  232. LFDUX f27, X, INCX
  233. LFDUX f28, X, INCX
  234. LFDUX f29, X, INCX
  235. LFDUX f30, X, INCX
  236. LFDUX f31, X, INCX
  237. fmr f16, f8
  238. fmr f17, f9
  239. fmr f18, f10
  240. fmr f19, f11
  241. fmr f20, f12
  242. fmr f21, f13
  243. fmr f22, f14
  244. fmr f23, f15
  245. bdz LL(120)
  246. .align 4
  247. LL(110):
  248. FADD f0, f0, f16
  249. fmr f16, f24
  250. FADD f1, f1, f17
  251. fmr f17, f25
  252. FADD f2, f2, f18
  253. fmr f18, f26
  254. FADD f3, f3, f19
  255. fmr f19, f27
  256. LFDUX f8, X, INCX
  257. LFDUX f9, X, INCX
  258. LFDUX f10, X, INCX
  259. LFDUX f11, X, INCX
  260. FADD f4, f4, f20
  261. fmr f20, f28
  262. FADD f5, f5, f21
  263. fmr f21, f29
  264. FADD f6, f6, f22
  265. fmr f22, f30
  266. FADD f7, f7, f23
  267. fmr f23, f31
  268. LFDUX f12, X, INCX
  269. LFDUX f13, X, INCX
  270. LFDUX f14, X, INCX
  271. LFDUX f15, X, INCX
  272. FADD f0, f0, f16
  273. fmr f16, f8
  274. FADD f1, f1, f17
  275. fmr f17, f9
  276. FADD f2, f2, f18
  277. fmr f18, f10
  278. FADD f3, f3, f19
  279. fmr f19, f11
  280. LFDUX f24, X, INCX
  281. LFDUX f25, X, INCX
  282. LFDUX f26, X, INCX
  283. LFDUX f27, X, INCX
  284. FADD f4, f4, f20
  285. fmr f20, f12
  286. FADD f5, f5, f21
  287. fmr f21, f13
  288. FADD f6, f6, f22
  289. fmr f22, f14
  290. FADD f7, f7, f23
  291. fmr f23, f15
  292. LFDUX f28, X, INCX
  293. LFDUX f29, X, INCX
  294. LFDUX f30, X, INCX
  295. LFDUX f31, X, INCX
  296. bdnz LL(110)
  297. .align 4
  298. LL(120):
  299. FADD f0, f0, f16
  300. fmr f16, f24
  301. FADD f1, f1, f17
  302. fmr f17, f25
  303. FADD f2, f2, f18
  304. fmr f18, f26
  305. FADD f3, f3, f19
  306. fmr f19, f27
  307. FADD f4, f4, f20
  308. fmr f20, f28
  309. FADD f5, f5, f21
  310. fmr f21, f29
  311. FADD f6, f6, f22
  312. fmr f22, f30
  313. FADD f7, f7, f23
  314. fmr f23, f31
  315. FADD f0, f0, f16
  316. FADD f1, f1, f17
  317. FADD f2, f2, f18
  318. FADD f3, f3, f19
  319. FADD f4, f4, f20
  320. FADD f5, f5, f21
  321. FADD f6, f6, f22
  322. FADD f7, f7, f23
  323. .align 4
  324. LL(150):
  325. andi. r0, N, 15
  326. mtspr CTR, r0
  327. beq LL(999)
  328. .align 4
  329. LL(160):
  330. LFDUX f8, X, INCX
  331. FADD f0, f0, f8
  332. bdnz LL(160)
  333. .align 4
  334. LL(999):
  335. FADD f0, f0, f1
  336. FADD f2, f2, f3
  337. FADD f4, f4, f5
  338. FADD f6, f6, f7
  339. FADD f0, f0, f2
  340. FADD f4, f4, f6
  341. FADD f1, f0, f4
  342. lfd f14, 0(SP)
  343. lfd f15, 8(SP)
  344. lfd f16, 16(SP)
  345. lfd f17, 24(SP)
  346. lfd f18, 32(SP)
  347. lfd f19, 40(SP)
  348. lfd f20, 48(SP)
  349. lfd f21, 56(SP)
  350. lfd f22, 64(SP)
  351. lfd f23, 72(SP)
  352. lfd f24, 80(SP)
  353. lfd f25, 88(SP)
  354. lfd f26, 96(SP)
  355. lfd f27, 104(SP)
  356. lfd f28, 112(SP)
  357. lfd f29, 120(SP)
  358. lfd f30, 128(SP)
  359. lfd f31, 136(SP)
  360. addi SP, SP, STACKSIZE
  361. blr
  362. EPILOGUE