You can not select more than 25 topics Topics must start with a chinese character,a letter or number, can include dashes ('-') and can be up to 35 characters long.

gemm_kernel_power3.S 30 kB

rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
rebase? (#1) * With the Intel compiler on Linux, prefer ifort for the final link step icc has known problems with mixed-language builds that ifort can handle just fine. Fixes #1956 * Rename operands to put lda on the input/output constraint list * Fix wrong constraints in inline assembly for #2009 * Fix inline assembly constraints rework indices to allow marking argument lda4 as input and output. For #2009 * Fix inline assembly constraints rework indices to allow marking argument lda as input and output. * Fix inline assembly constraints * Fix inline assembly constraints * Fix inline assembly constraints in Bulldozer TRSM kernels rework indices to allow marking i,as and bs as both input and output (marked operand n1 as well for simplicity). For #2009 * Correct range_n limiting same bug as seen in #1388, somehow missed in corresponding PR #1389 * Allow multithreading TRMV again revert workaround introduced for issue #1332 as the actual cause appears to be my incorrect fix from #1262 (see #1388) * Fix error introduced during cleanup * Reduce list of kernels in the dynamic arch build to make compilation complete reliably within the 1h limit again * init * move fix to right place * Fix missing -c option in AVX512 test * Fix AVX512 test always returning false due to missing compiler option * Make x86_32 imply NO_AVX2, NO_AVX512 in addition to NO_AVX fixes #2033 * Keep xcode8.3 for osx BINARY=32 build as xcode10 deprecated i386 * Make sure that AVX512 is disabled in 32bit builds for #2033 * Improve handling of NO_STATIC and NO_SHARED to avoid surprises from defining either as zero. Fixes #2035 by addressing some concerns from #1422 * init * address warning introed with #1814 et al * Restore locking optimizations for OpenMP case restore another accidentally dropped part of #1468 that was missed in #2004 to address performance regression reported in #1461 * HiSilicon tsv110 CPUs optimization branch add HiSilicon tsv110 CPUs optimization branch * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * add TARGET support for HiSilicon tsv110 CPUs * Fix module definition conflicts between LAPACK and ReLAPACK for #2043 * Do not compile in AVX512 check if AVX support is disabled xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway * ctest.c : add __POWERPC__ for PowerMac * Fix crash in sgemm SSE/nano kernel on x86_64 Fix bug #2047. Signed-off-by: Celelibi <celelibi@gmail.com> * param.h : enable defines for PPC970 on DarwinOS fixes: gemm.c: In function 'sgemm_': ../common_param.h:981:18: error: 'SGEMM_DEFAULT_P' undeclared (first use in this function) #define SGEMM_P SGEMM_DEFAULT_P ^ * common_power.h: force DCBT_ARG 0 on PPC970 Darwin without this, we see ../kernel/power/gemv_n.S:427:Parameter syntax error and many more similar entries that relates to this assembly command dcbt 8, r24, r18 this change makes the DCBT_ARG = 0 and openblas builds through to completion on PowerMac 970 Tests pass * Make TARGET=GENERIC compatible with DYNAMIC_ARCH=1 for issue #2048 * make DYNAMIC_ARCH=1 package work on TSV110. * make DYNAMIC_ARCH=1 package work on TSV110 * Add Intel Denverton for #2048 * Add Intel Denverton * Change 64-bit detection as explained in #2056 * Trivial typo fix as suggested in #2022 * Disable the AVX512 DGEMM kernel (again) Due to as yet unresolved errors seen in #1955 and #2029 * Use POSIX getenv on Cygwin The Windows-native GetEnvironmentVariable cannot be relied on, as Cygwin does not always copy environment variables set through Cygwin to the Windows environment block, particularly after fork(). * Fix for #2063: The DllMain used in Cygwin did not run the thread memory pool cleanup upon THREAD_DETACH which is needed when compiled with USE_TLS=1. * Also call CloseHandle on each thread, as well as on the event so as to not leak thread handles. * AIX asm syntax changes needed for shared object creation * power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself * Expose CBLAS interfaces for I?MIN and I?MAX * Build CBLAS interfaces for I?MIN and I?MAX * Add declarations for ?sum and cblas_?sum * Add interface for ?sum (derived from ?asum) * Add ?sum * Add implementations of ssum/dsum and csum/zsum as trivial copies of asum/zsasum with the fabs calls replaced by fmov to preserve code structure * Add ARM implementations of ?sum (trivial copies of the respective ?asum with the fabs calls removed) * Add ARM64 implementations of ?sum as trivial copies of the respective ?asum kernels with the fabs calls removed * Add ia64 implementation of ?sum as trivial copy of asum with the fabs calls removed * Add MIPS implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add MIPS64 implementation of ?sum as trivial copy of ?asum with the fabs replaced by mov to preserve code structure * Add POWER implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmr to preserve code structure * Add SPARC implementation of ?sum as trivial copy of ?asum with the fabs replaced by fmov to preserve code structure * Add x86 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add x86_64 implementation of ?sum as trivial copy of ?asum with the fabs calls removed * Add ZARCH implementation of ?sum as trivial copies of the respective ?asum kernels with the ABS and vflpsb calls removed * Detect 32bit environment on 64bit ARM hardware for #2056, using same approach as #2058 * Add cmake defaults for ?sum kernels * Add ?sum * Add ?sum definitions for generic kernel * Add declarations for ?sum * Add -lm and disable EXPRECISION support on *BSD fixes #2075 * Add in runtime CPU detection for POWER. * snprintf define consolidated to common.h * Support INTERFACE64=1 * Add support for INTERFACE64 and fix XERBLA calls 1. Replaced all instances of "int" with "blasint" 2. Added string length as "hidden" third parameter in calls to fortran XERBLA * Correct length of name string in xerbla call * Avoid out-of-bounds accesses in LAPACK EIG tests see https://github.com/Reference-LAPACK/lapack/issues/333 * Correct INFO=4 condition * Disable reallocation of work array in xSYTRF as it appears to cause memory management problems (seen in the LAPACK tests) * Disable repeated recursion on Ab_BR in ReLAPACK xGBTRF due to crashes in LAPACK tests * sgemm/strmm * Update Changelog with changes from 0.3.6 * Increment version to 0.3.7.dev * Increment version to 0.3.7.dev * Misc. typo fixes Found via `codespell -q 3 -w -L ith,als,dum,nd,amin,nto,wis,ba -S ./relapack,./kernel,./lapack-netlib` * Correct argument of CPU_ISSET for glibc <2.5 fixes #2104 * conflict resolve * Revert reference/ fixes * Revert Changelog.txt typos * Disable the SkyLakeX DGEMMITCOPY kernel as well as a stopgap measure for https://github.com/numpy/numpy/issues/13401 as mentioned in #1955 * Disable DGEMMINCOPY as well for now #1955 * init * Fix errors in cpu enumeration with glibc 2.6 for #2114 * Change two http links to https Closes #2109 * remove redundant code #2113 * Set up CI with Azure Pipelines [skip ci] * TST: add native POWER8 to CI * add native POWER8 testing to Travis CI matrix with ppc64le os entry * Update link to IBM MASS library, update cpu support status * first try migrating one of the arm builds from travis * fix tabbing in azure commands * Update azure-pipelines.yml take out offending lines (although stolen from https://github.com/conda-forge/opencv-feedstock azure-pipelines fiie) * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * Update azure-pipelines.yml * DOC: Add Azure CI status badge * Add ARMV6 build to azure CI setup (#2122) using aytekinar's Alpine image and docker script from the Travis setup [skip ci] * TST: Azure manylinux1 & clean-up * remove some of the steps & comments from the original Azure yml template * modify the trigger section to use develop since OpenBLAS primarily uses this branch; use the same batching behavior as downstream projects NumPy/ SciPy * remove Travis emulated ARMv6 gcc build because this now happens in Azure * use documented Ubuntu vmImage name for Azure and add in a manylinux1 test run to the matrix [skip appveyor] * Add NO_AFFINITY to available options on Linux, and set it to ON to match the gmake default. Fixes second part of #2114 * Replace ISMIN and ISAMIN kernels on all x86_64 platforms (#2125) * Mark iamax_sse.S as unsuitable for MIN due to issue #2116 * Use iamax.S rather than iamax_sse.S for ISMIN/ISAMIN on all x86_64 as workaround for #2116 * Move ARMv8 gcc build from Travis to Azure * Move ARMv8 gcc build from Travis to Azure * Update .travis.yml * Test drone CI * install make * remove sudo * Install gcc * Install perl * Install gfortran and add a clang job * gfortran->gcc-gfortran * Switch to ubuntu and parallel jobs * apt update * Fix typo * update yes * no need of gcc in clang build * Add a cmake build as well * Add cmake builds and print options * build without lapack on cmake * parallel build * See if ubuntu 19.04 fixes the ICE * Remove qemu armv8 builds * arm32 build * Fix typo * TST: add SkylakeX AVX512 CI test * adapt the C-level reproducer code for some recent SkylakeX AVX512 kernel issues, provided by Isuru Fernando and modified by Martin Kroeker, for usage in the utest suite * add an Intel SDE SkylakeX emulation utest run to the Azure CI matrix; a custom Docker build was required because Ubuntu image provided by Azure does not support AVX512VL instructions * Add option USE_LOCKING for single-threaded build with locking support for calling from concurrent threads * Add option USE_LOCKING for single-threaded build with locking support * Add option USE_LOCKING for SMP-like locking in USE_THREAD=0 builds * Add option USE_LOCKING but keep default settings intact * Remove unrelated change * Do not try ancient PGI hacks with recent versions of that compiler should fix #2139 * Build and run utests in any case, they do their own checks for fortran availability * Add softfp support in min/max kernels fix for #1912 * Revert "Add softfp support in min/max kernels" * Separate implementations of AMAX and IAMAX on arm As noted in #1912 and comment on #1942, the combined implementation happens to "do the right thing" on hardfp, but cannot return both value and index on softfp where they would have to share the return register * Ensure correct output for DAMAX with softfp * Use generic kernels for complex (I)AMAX to support softfp * improved zgemm power9 based on power8 * upload thread safety test folder * hook up c++ thread safety test (main Makefile) * add c++ thread test option to Makefile.rule * Document NO_AVX512 for #2151 * sgemm pipeline improved, zgemm rewritten without inner packs, ABI lxvx v20 fixed with vs52 * Fix detection of AVX512 capable compilers in getarch 21eda8b5 introduced a check in getarch.c to test if the compiler is capable of AVX512. This check currently fails, since the used __AVX2__ macro is only defined if getarch itself was compiled with AVX2/AVX512 support. Make sure this is the case by building getarch with -march=native on x86_64. It is only supposed to run on the build host anyway. * c_check: Unlink correct file * power9 zgemm ztrmm optimized * conflict resolve * Add gfortran workaround for ABI violations in LAPACKE for #2154 (see gcc bug 90329) * Add gfortran workaround for ABI violations for #2154 (see gcc bug 90329) * Add gfortran workaround for potential ABI violation for #2154 * Update fc.cmake * Remove any inadvertent use of -march=native from DYNAMIC_ARCH builds from #2143, -march=native precludes use of more specific options like -march=skylake-avx512 in individual kernels, and defeats the purpose of dynamic arch anyway. * Avoid unintentional activation of TLS code via USE_TLS=0 fixes #2149 * Do not force gcc options on non-gcc compilers fixes compile failure with pgi 18.10 as reported on OpenBLAS-users * Update Makefile.x86_64 * Zero ecx with a mov instruction PGI assembler does not like the initialization in the constraints. * Fix mov syntax * new sgemm 8x16 * Update dtrmm_kernel_16x4_power8.S * PGI compiler does not like -march=native * Fix build on FreeBSD/powerpc64. Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> * Fix build for PPC970 on FreeBSD pt. 1 FreeBSD needs DCBT_ARG=0 as well. * Fix build for PPC970 on FreeBSD pt.2 FreeBSD needs those macros too. * cgemm/ctrmm power9 * Utest needs CBLAS but not necessarily FORTRAN * Add mingw builds to Appveyor config * Add getarch flags to disable AVX on x86 (and other small fixes to match Makefile behaviour) * Make disabling DYNAMIC_ARCH on unsupported systems work needs to be unset in the cache for the change to have any effect * Mingw32 needs leading underscore on object names (also copy BUNDERSCORE settings for FORTRAN from the corresponding Makefile)
7 years ago
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664
  1. /*********************************************************************/
  2. /* Copyright 2009, 2010 The University of Texas at Austin. */
  3. /* All rights reserved. */
  4. /* */
  5. /* Redistribution and use in source and binary forms, with or */
  6. /* without modification, are permitted provided that the following */
  7. /* conditions are met: */
  8. /* */
  9. /* 1. Redistributions of source code must retain the above */
  10. /* copyright notice, this list of conditions and the following */
  11. /* disclaimer. */
  12. /* */
  13. /* 2. Redistributions in binary form must reproduce the above */
  14. /* copyright notice, this list of conditions and the following */
  15. /* disclaimer in the documentation and/or other materials */
  16. /* provided with the distribution. */
  17. /* */
  18. /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
  19. /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
  20. /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
  21. /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
  22. /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
  23. /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
  24. /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
  25. /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
  26. /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
  27. /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
  28. /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
  29. /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
  30. /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
  31. /* POSSIBILITY OF SUCH DAMAGE. */
  32. /* */
  33. /* The views and conclusions contained in the software and */
  34. /* documentation are those of the authors and should not be */
  35. /* interpreted as representing official policies, either expressed */
  36. /* or implied, of The University of Texas at Austin. */
  37. /*********************************************************************/
  38. #define ASSEMBLER
  39. #include "common.h"
  40. #ifndef __64BIT__
  41. #define LOAD lwz
  42. #else
  43. #define LOAD ld
  44. #endif
  45. #ifdef __64BIT__
  46. #define STACKSIZE 320
  47. #define ALPHA 296(SP)
  48. #define FZERO 304(SP)
  49. #else
  50. #define STACKSIZE 240
  51. #define ALPHA 224(SP)
  52. #define FZERO 232(SP)
  53. #endif
  54. #define M r3
  55. #define N r4
  56. #define K r5
  57. #if defined(linux) || defined(__FreeBSD__)
  58. #ifndef __64BIT__
  59. #define A r6
  60. #define B r7
  61. #define C r8
  62. #define LDC r9
  63. #else
  64. #define A r7
  65. #define B r8
  66. #define C r9
  67. #define LDC r10
  68. #endif
  69. #endif
  70. #if defined(_AIX) || defined(__APPLE__)
  71. #if !defined(__64BIT__) && defined(DOUBLE)
  72. #define A r8
  73. #define B r9
  74. #define C r10
  75. #define LDC r7
  76. #else
  77. #define A r7
  78. #define B r8
  79. #define C r9
  80. #define LDC r10
  81. #endif
  82. #endif
  83. #define I r21
  84. #define J r22
  85. #define AO r23
  86. #define BO r24
  87. #define CO1 r25
  88. #define CO2 r26
  89. #define CO3 r27
  90. #define CO4 r28
  91. #define PREA r29
  92. #define PREB r30
  93. #define PREC r31
  94. #ifndef NEEDPARAM
  95. #ifndef DOUBLE
  96. #include "../sparam.h"
  97. #else
  98. #include "../dparam.h"
  99. #endif
  100. PROLOGUE
  101. PROFCODE
  102. addi SP, SP, -STACKSIZE
  103. li r0, 0
  104. stfd f14, 0(SP)
  105. stfd f15, 8(SP)
  106. stfd f16, 16(SP)
  107. stfd f17, 24(SP)
  108. stfd f18, 32(SP)
  109. stfd f19, 40(SP)
  110. stfd f20, 48(SP)
  111. stfd f21, 56(SP)
  112. stfd f22, 64(SP)
  113. stfd f23, 72(SP)
  114. stfd f24, 80(SP)
  115. stfd f25, 88(SP)
  116. stfd f26, 96(SP)
  117. stfd f27, 104(SP)
  118. stfd f28, 112(SP)
  119. stfd f29, 120(SP)
  120. stfd f30, 128(SP)
  121. stfd f31, 136(SP)
  122. #ifdef __64BIT__
  123. std r31, 144(SP)
  124. std r30, 152(SP)
  125. std r29, 160(SP)
  126. std r28, 168(SP)
  127. std r27, 176(SP)
  128. std r26, 184(SP)
  129. std r25, 192(SP)
  130. std r24, 200(SP)
  131. std r23, 208(SP)
  132. std r22, 216(SP)
  133. std r21, 224(SP)
  134. #else
  135. stw r31, 144(SP)
  136. stw r30, 148(SP)
  137. stw r29, 152(SP)
  138. stw r28, 156(SP)
  139. stw r27, 160(SP)
  140. stw r26, 164(SP)
  141. stw r25, 168(SP)
  142. stw r24, 172(SP)
  143. stw r23, 176(SP)
  144. stw r22, 180(SP)
  145. stw r21, 184(SP)
  146. #endif
  147. stfd f1, ALPHA
  148. stw r0, FZERO
  149. #if defined(_AIX) || defined(__APPLE__)
  150. #if !defined(__64BIT__) && defined(DOUBLE)
  151. lwz LDC, FRAMESLOT(0) + STACKSIZE(SP)
  152. #endif
  153. #endif
  154. slwi LDC, LDC, BASE_SHIFT
  155. cmpwi cr0, M, 0
  156. ble LL(999)
  157. cmpwi cr0, N, 0
  158. ble LL(999)
  159. cmpwi cr0, K, 0
  160. ble LL(999)
  161. #ifndef PREFETCHTEST
  162. li PREA, (16 * 5 * SIZE + 16)
  163. li PREB, (16 * 5 * SIZE + 16)
  164. li PREC, 4 * SIZE
  165. #else
  166. #if defined(linux) || defined(__FreeBSD__)
  167. #ifndef __64BIT__
  168. mr PREA, r10
  169. lwz PREB, FRAMESLOT(0) + STACKSIZE(SP)
  170. lwz PREC, FRAMESLOT(1) + STACKSIZE(SP)
  171. #else
  172. ld PREA, FRAMESLOT(0) + STACKSIZE(SP)
  173. ld PREB, FRAMESLOT(1) + STACKSIZE(SP)
  174. ld PREC, FRAMESLOT(2) + STACKSIZE(SP)
  175. #endif
  176. #endif
  177. #if defined(_AIX) || defined(__APPLE__)
  178. #ifdef __64BIT__
  179. ld PREA, FRAMESLOT(0) + STACKSIZE(SP)
  180. ld PREB, FRAMESLOT(1) + STACKSIZE(SP)
  181. ld PREC, FRAMESLOT(2) + STACKSIZE(SP)
  182. #else
  183. #ifdef DOUBLE
  184. lwz PREA, FRAMESLOT(1) + STACKSIZE(SP)
  185. lwz PREB, FRAMESLOT(2) + STACKSIZE(SP)
  186. lwz PREC, FRAMESLOT(3) + STACKSIZE(SP)
  187. #else
  188. lwz PREA, FRAMESLOT(0) + STACKSIZE(SP)
  189. lwz PREB, FRAMESLOT(1) + STACKSIZE(SP)
  190. lwz PREC, FRAMESLOT(2) + STACKSIZE(SP)
  191. #endif
  192. #endif
  193. #endif
  194. #endif
  195. lfs f0, FZERO
  196. srawi. J, N, 2
  197. ble LL(40)
  198. .align 4
  199. LL(10):
  200. mr CO1, C
  201. add CO2, C, LDC
  202. add CO3, CO2, LDC
  203. add CO4, CO3, LDC
  204. fmr f1, f0
  205. fmr f2, f0
  206. fmr f3, f0
  207. fmr f4, f0
  208. fmr f5, f0
  209. fmr f6, f0
  210. fmr f7, f0
  211. fmr f8, f0
  212. fmr f9, f0
  213. fmr f10, f0
  214. fmr f11, f0
  215. fmr f12, f0
  216. fmr f13, f0
  217. fmr f14, f0
  218. fmr f15, f0
  219. srawi. I, M, 2
  220. mr AO, A
  221. add C, CO4, LDC
  222. ble LL(20)
  223. .align 4
  224. LL(11):
  225. LFD f16, 0 * SIZE(AO)
  226. LFD f17, 1 * SIZE(AO)
  227. LFD f18, 2 * SIZE(AO)
  228. LFD f19, 3 * SIZE(AO)
  229. LFD f20, 0 * SIZE(B)
  230. LFD f21, 1 * SIZE(B)
  231. LFD f22, 2 * SIZE(B)
  232. LFD f23, 3 * SIZE(B)
  233. LFD f24, 4 * SIZE(AO)
  234. LFD f25, 5 * SIZE(AO)
  235. LFD f26, 6 * SIZE(AO)
  236. LFD f27, 7 * SIZE(AO)
  237. #if 0
  238. PREFETCH_C1
  239. PREFETCH_C2
  240. PREFETCH_C3
  241. PREFETCH_C4
  242. #endif
  243. srawi. r0, K, 2
  244. mtspr CTR, r0
  245. mr BO, B
  246. ble LL(15)
  247. .align 4
  248. LL(12):
  249. fmadd f0, f16, f20, f0
  250. fmadd f4, f16, f21, f4
  251. LFD f28, 4 * SIZE(BO)
  252. fmadd f8, f16, f22, f8
  253. fmadd f12, f16, f23, f12
  254. LFD f16, 8 * SIZE(AO)
  255. fmadd f1, f17, f20, f1
  256. fmadd f5, f17, f21, f5
  257. LFD f29, 5 * SIZE(BO)
  258. fmadd f9, f17, f22, f9
  259. fmadd f13, f17, f23, f13
  260. LFD f17, 9 * SIZE(AO)
  261. fmadd f2, f18, f20, f2
  262. fmadd f6, f18, f21, f6
  263. LFD f30, 6 * SIZE(BO)
  264. fmadd f10, f18, f22, f10
  265. fmadd f14, f18, f23, f14
  266. LFD f18, 10 * SIZE(AO)
  267. fmadd f3, f19, f20, f3
  268. fmadd f7, f19, f21, f7
  269. LFD f31, 7 * SIZE(BO)
  270. fmadd f11, f19, f22, f11
  271. fmadd f15, f19, f23, f15
  272. LFD f19, 11 * SIZE(AO)
  273. fmadd f0, f24, f28, f0
  274. fmadd f4, f24, f29, f4
  275. LFD f20, 8 * SIZE(BO)
  276. fmadd f8, f24, f30, f8
  277. fmadd f12, f24, f31, f12
  278. LFD f24, 12 * SIZE(AO)
  279. fmadd f1, f25, f28, f1
  280. fmadd f5, f25, f29, f5
  281. LFD f21, 9 * SIZE(BO)
  282. fmadd f9, f25, f30, f9
  283. fmadd f13, f25, f31, f13
  284. LFD f25, 13 * SIZE(AO)
  285. fmadd f2, f26, f28, f2
  286. fmadd f6, f26, f29, f6
  287. LFD f22, 10 * SIZE(BO)
  288. fmadd f10, f26, f30, f10
  289. fmadd f14, f26, f31, f14
  290. LFD f26, 14 * SIZE(AO)
  291. fmadd f3, f27, f28, f3
  292. fmadd f7, f27, f29, f7
  293. LFD f23, 11 * SIZE(BO)
  294. fmadd f11, f27, f30, f11
  295. fmadd f15, f27, f31, f15
  296. LFD f27, 15 * SIZE(AO)
  297. fmadd f0, f16, f20, f0
  298. fmadd f4, f16, f21, f4
  299. LFD f28, 12 * SIZE(BO)
  300. fmadd f8, f16, f22, f8
  301. fmadd f12, f16, f23, f12
  302. LFDU f16, 16 * SIZE(AO)
  303. fmadd f1, f17, f20, f1
  304. fmadd f5, f17, f21, f5
  305. LFD f29, 13 * SIZE(BO)
  306. fmadd f9, f17, f22, f9
  307. fmadd f13, f17, f23, f13
  308. LFD f17, 1 * SIZE(AO)
  309. fmadd f2, f18, f20, f2
  310. fmadd f6, f18, f21, f6
  311. LFD f30, 14 * SIZE(BO)
  312. fmadd f10, f18, f22, f10
  313. fmadd f14, f18, f23, f14
  314. LFD f18, 2 * SIZE(AO)
  315. fmadd f3, f19, f20, f3
  316. fmadd f7, f19, f21, f7
  317. LFD f31, 15 * SIZE(BO)
  318. fmadd f11, f19, f22, f11
  319. fmadd f15, f19, f23, f15
  320. LFD f19, 3 * SIZE(AO)
  321. fmadd f0, f24, f28, f0
  322. fmadd f4, f24, f29, f4
  323. LFDU f20, 16 * SIZE(BO)
  324. fmadd f8, f24, f30, f8
  325. fmadd f12, f24, f31, f12
  326. LFD f24, 4 * SIZE(AO)
  327. fmadd f1, f25, f28, f1
  328. fmadd f5, f25, f29, f5
  329. LFD f21, 1 * SIZE(BO)
  330. fmadd f9, f25, f30, f9
  331. fmadd f13, f25, f31, f13
  332. LFD f25, 5 * SIZE(AO)
  333. fmadd f2, f26, f28, f2
  334. fmadd f6, f26, f29, f6
  335. LFD f22, 2 * SIZE(BO)
  336. fmadd f10, f26, f30, f10
  337. fmadd f14, f26, f31, f14
  338. LFD f26, 6 * SIZE(AO)
  339. fmadd f3, f27, f28, f3
  340. fmadd f7, f27, f29, f7
  341. LFD f23, 3 * SIZE(BO)
  342. fmadd f11, f27, f30, f11
  343. fmadd f15, f27, f31, f15
  344. LFD f27, 7 * SIZE(AO)
  345. bdnz LL(12)
  346. .align 4
  347. LL(15):
  348. andi. r0, K, 3
  349. lfd f30, ALPHA
  350. lfs f31, FZERO
  351. mtspr CTR, r0
  352. ble+ LL(18)
  353. .align 4
  354. LL(16):
  355. fmadd f0, f16, f20, f0
  356. fmadd f4, f16, f21, f4
  357. fmadd f8, f16, f22, f8
  358. fmadd f12, f16, f23, f12
  359. LFD f16, 4 * SIZE(AO)
  360. fmadd f1, f17, f20, f1
  361. fmadd f5, f17, f21, f5
  362. fmadd f9, f17, f22, f9
  363. fmadd f13, f17, f23, f13
  364. LFD f17, 5 * SIZE(AO)
  365. fmadd f2, f18, f20, f2
  366. fmadd f6, f18, f21, f6
  367. fmadd f10, f18, f22, f10
  368. fmadd f14, f18, f23, f14
  369. LFD f18, 6 * SIZE(AO)
  370. fmadd f3, f19, f20, f3
  371. LFD f20, 4 * SIZE(BO)
  372. fmadd f7, f19, f21, f7
  373. LFD f21, 5 * SIZE(BO)
  374. fmadd f11, f19, f22, f11
  375. LFD f22, 6 * SIZE(BO)
  376. fmadd f15, f19, f23, f15
  377. LFD f19, 7 * SIZE(AO)
  378. LFD f23, 7 * SIZE(BO)
  379. addi BO, BO, 4 * SIZE
  380. addi AO, AO, 4 * SIZE
  381. bdnz LL(16)
  382. .align 4
  383. LL(18):
  384. LFD f16, 0 * SIZE(CO1)
  385. LFD f17, 1 * SIZE(CO1)
  386. LFD f18, 2 * SIZE(CO1)
  387. LFD f19, 3 * SIZE(CO1)
  388. LFD f20, 0 * SIZE(CO2)
  389. LFD f21, 1 * SIZE(CO2)
  390. LFD f22, 2 * SIZE(CO2)
  391. LFD f23, 3 * SIZE(CO2)
  392. fmadd f0, f0, f30, f16
  393. LFD f16, 0 * SIZE(CO3)
  394. fmadd f1, f1, f30, f17
  395. LFD f17, 1 * SIZE(CO3)
  396. fmadd f2, f2, f30, f18
  397. LFD f18, 2 * SIZE(CO3)
  398. fmadd f3, f3, f30, f19
  399. LFD f19, 3 * SIZE(CO3)
  400. fmadd f4, f4, f30, f20
  401. LFD f20, 0 * SIZE(CO4)
  402. fmadd f5, f5, f30, f21
  403. LFD f21, 1 * SIZE(CO4)
  404. fmadd f6, f6, f30, f22
  405. LFD f22, 2 * SIZE(CO4)
  406. fmadd f7, f7, f30, f23
  407. LFD f23, 3 * SIZE(CO4)
  408. fmadd f8, f8, f30, f16
  409. fmadd f9, f9, f30, f17
  410. STFD f0, 0 * SIZE(CO1)
  411. fmadd f10, f10, f30, f18
  412. fmadd f11, f11, f30, f19
  413. STFD f1, 1 * SIZE(CO1)
  414. fmadd f12, f12, f30, f20
  415. fmadd f13, f13, f30, f21
  416. STFD f2, 2 * SIZE(CO1)
  417. fmadd f14, f14, f30, f22
  418. fmadd f15, f15, f30, f23
  419. STFD f3, 3 * SIZE(CO1)
  420. STFD f4, 0 * SIZE(CO2)
  421. fmr f0, f31
  422. fmr f1, f31
  423. STFD f5, 1 * SIZE(CO2)
  424. fmr f2, f31
  425. fmr f3, f31
  426. STFD f6, 2 * SIZE(CO2)
  427. fmr f4, f31
  428. fmr f5, f31
  429. STFD f7, 3 * SIZE(CO2)
  430. fmr f6, f31
  431. fmr f7, f31
  432. STFD f8, 0 * SIZE(CO3)
  433. STFD f9, 1 * SIZE(CO3)
  434. addi CO1, CO1, 4 * SIZE
  435. fmr f8, f31
  436. fmr f9, f31
  437. STFD f10, 2 * SIZE(CO3)
  438. STFD f11, 3 * SIZE(CO3)
  439. addi CO2, CO2, 4 * SIZE
  440. fmr f10, f31
  441. fmr f11, f31
  442. STFD f12, 0 * SIZE(CO4)
  443. STFD f13, 1 * SIZE(CO4)
  444. addi CO3, CO3, 4 * SIZE
  445. fmr f12, f31
  446. fmr f13, f31
  447. STFD f14, 2 * SIZE(CO4)
  448. STFD f15, 3 * SIZE(CO4)
  449. addi CO4, CO4, 4 * SIZE
  450. fmr f14, f31
  451. fmr f15, f31
  452. addic. I, I, -1
  453. bgt+ LL(11)
  454. .align 4
  455. LL(20):
  456. andi. I, M, 2
  457. ble LL(30)
  458. LFD f16, 0 * SIZE(AO)
  459. LFD f17, 1 * SIZE(AO)
  460. LFD f18, 2 * SIZE(AO)
  461. LFD f19, 3 * SIZE(AO)
  462. LFD f20, 0 * SIZE(B)
  463. LFD f21, 1 * SIZE(B)
  464. LFD f22, 2 * SIZE(B)
  465. LFD f23, 3 * SIZE(B)
  466. LFD f24, 4 * SIZE(B)
  467. LFD f25, 5 * SIZE(B)
  468. LFD f26, 6 * SIZE(B)
  469. LFD f27, 7 * SIZE(B)
  470. srawi. r0, K, 2
  471. mtspr CTR, r0
  472. mr BO, B
  473. ble LL(25)
  474. .align 5
  475. LL(22):
  476. fmadd f0, f16, f20, f0
  477. fmadd f1, f17, f20, f1
  478. fmadd f4, f16, f21, f4
  479. fmadd f5, f17, f21, f5
  480. fmadd f8, f16, f22, f8
  481. fmadd f9, f17, f22, f9
  482. fmadd f12, f16, f23, f12
  483. fmadd f13, f17, f23, f13
  484. LFD f20, 8 * SIZE(BO)
  485. LFD f21, 9 * SIZE(BO)
  486. LFD f22, 10 * SIZE(BO)
  487. LFD f23, 11 * SIZE(BO)
  488. fmadd f2, f18, f24, f2
  489. fmadd f3, f19, f24, f3
  490. fmadd f6, f18, f25, f6
  491. fmadd f7, f19, f25, f7
  492. fmadd f10, f18, f26, f10
  493. fmadd f11, f19, f26, f11
  494. fmadd f14, f18, f27, f14
  495. fmadd f15, f19, f27, f15
  496. LFD f16, 4 * SIZE(AO)
  497. LFD f17, 5 * SIZE(AO)
  498. LFD f18, 6 * SIZE(AO)
  499. LFD f19, 7 * SIZE(AO)
  500. fmadd f0, f16, f20, f0
  501. fmadd f1, f17, f20, f1
  502. fmadd f4, f16, f21, f4
  503. fmadd f5, f17, f21, f5
  504. LFD f24, 12 * SIZE(BO)
  505. LFD f25, 13 * SIZE(BO)
  506. LFD f26, 14 * SIZE(BO)
  507. LFD f27, 15 * SIZE(BO)
  508. fmadd f8, f16, f22, f8
  509. fmadd f9, f17, f22, f9
  510. fmadd f12, f16, f23, f12
  511. fmadd f13, f17, f23, f13
  512. LFD f20, 16 * SIZE(BO)
  513. LFD f21, 17 * SIZE(BO)
  514. LFD f22, 18 * SIZE(BO)
  515. LFD f23, 19 * SIZE(BO)
  516. fmadd f2, f18, f24, f2
  517. fmadd f3, f19, f24, f3
  518. fmadd f6, f18, f25, f6
  519. fmadd f7, f19, f25, f7
  520. fmadd f10, f18, f26, f10
  521. fmadd f11, f19, f26, f11
  522. fmadd f14, f18, f27, f14
  523. fmadd f15, f19, f27, f15
  524. LFD f16, 8 * SIZE(AO)
  525. LFD f17, 9 * SIZE(AO)
  526. LFD f18, 10 * SIZE(AO)
  527. LFD f19, 11 * SIZE(AO)
  528. LFD f24, 20 * SIZE(BO)
  529. LFD f25, 21 * SIZE(BO)
  530. LFD f26, 22 * SIZE(BO)
  531. LFD f27, 23 * SIZE(BO)
  532. addi AO, AO, 8 * SIZE
  533. addi BO, BO, 16 * SIZE
  534. DCBT(BO, PREB)
  535. bdnz LL(22)
  536. fadd f0, f2, f0
  537. fadd f1, f3, f1
  538. fadd f4, f6, f4
  539. fadd f5, f7, f5
  540. fadd f8, f10, f8
  541. fadd f9, f11, f9
  542. fadd f12, f14, f12
  543. fadd f13, f15, f13
  544. .align 4
  545. LL(25):
  546. lfd f30, ALPHA
  547. andi. r0, K, 3
  548. mtspr CTR, r0
  549. ble+ LL(28)
  550. .align 4
  551. LL(26):
  552. fmadd f0, f16, f20, f0
  553. fmadd f1, f17, f20, f1
  554. fmadd f4, f16, f21, f4
  555. fmadd f5, f17, f21, f5
  556. fmadd f8, f16, f22, f8
  557. fmadd f9, f17, f22, f9
  558. fmadd f12, f16, f23, f12
  559. fmadd f13, f17, f23, f13
  560. LFD f16, 2 * SIZE(AO)
  561. LFD f17, 3 * SIZE(AO)
  562. LFD f20, 4 * SIZE(BO)
  563. LFD f21, 5 * SIZE(BO)
  564. LFD f22, 6 * SIZE(BO)
  565. LFD f23, 7 * SIZE(BO)
  566. addi BO, BO, 4 * SIZE
  567. addi AO, AO, 2 * SIZE
  568. bdnz LL(26)
  569. .align 4
  570. LL(28):
  571. LFD f16, 0 * SIZE(CO1)
  572. LFD f17, 1 * SIZE(CO1)
  573. LFD f18, 0 * SIZE(CO2)
  574. LFD f19, 1 * SIZE(CO2)
  575. fmadd f0, f0, f30, f16
  576. fmadd f1, f1, f30, f17
  577. fmadd f4, f4, f30, f18
  578. fmadd f5, f5, f30, f19
  579. LFD f20, 0 * SIZE(CO3)
  580. LFD f21, 1 * SIZE(CO3)
  581. LFD f22, 0 * SIZE(CO4)
  582. LFD f23, 1 * SIZE(CO4)
  583. fmadd f8, f8, f30, f20
  584. fmadd f9, f9, f30, f21
  585. fmadd f12, f12, f30, f22
  586. fmadd f13, f13, f30, f23
  587. STFD f0, 0 * SIZE(CO1)
  588. STFD f1, 1 * SIZE(CO1)
  589. STFD f4, 0 * SIZE(CO2)
  590. STFD f5, 1 * SIZE(CO2)
  591. lfs f0, FZERO
  592. fmr f1, f0
  593. fmr f2, f0
  594. fmr f3, f0
  595. STFD f8, 0 * SIZE(CO3)
  596. STFD f9, 1 * SIZE(CO3)
  597. STFD f12, 0 * SIZE(CO4)
  598. STFD f13, 1 * SIZE(CO4)
  599. fmr f4, f0
  600. fmr f5, f0
  601. fmr f6, f0
  602. fmr f7, f0
  603. fmr f8, f0
  604. fmr f9, f0
  605. fmr f10, f0
  606. fmr f11, f0
  607. fmr f12, f0
  608. fmr f13, f0
  609. fmr f14, f0
  610. fmr f15, f0
  611. addi CO1, CO1, 2 * SIZE
  612. addi CO2, CO2, 2 * SIZE
  613. addi CO3, CO3, 2 * SIZE
  614. addi CO4, CO4, 2 * SIZE
  615. .align 4
  616. LL(30):
  617. andi. I, M, 1
  618. ble LL(39)
  619. LFD f16, 0 * SIZE(AO)
  620. LFD f17, 1 * SIZE(AO)
  621. LFD f18, 2 * SIZE(AO)
  622. LFD f19, 3 * SIZE(AO)
  623. LFD f20, 0 * SIZE(B)
  624. LFD f21, 1 * SIZE(B)
  625. LFD f22, 2 * SIZE(B)
  626. LFD f23, 3 * SIZE(B)
  627. LFD f24, 4 * SIZE(B)
  628. LFD f25, 5 * SIZE(B)
  629. LFD f26, 6 * SIZE(B)
  630. LFD f27, 7 * SIZE(B)
  631. srawi. r0, K, 2
  632. mtspr CTR, r0
  633. mr BO, B
  634. ble LL(35)
  635. .align 5
  636. LL(32):
  637. fmadd f0, f16, f20, f0
  638. fmadd f4, f16, f21, f4
  639. fmadd f8, f16, f22, f8
  640. fmadd f12, f16, f23, f12
  641. LFD f20, 8 * SIZE(BO)
  642. LFD f21, 9 * SIZE(BO)
  643. LFD f22, 10 * SIZE(BO)
  644. LFD f23, 11 * SIZE(BO)
  645. fmadd f1, f17, f24, f1
  646. fmadd f5, f17, f25, f5
  647. fmadd f9, f17, f26, f9
  648. fmadd f13, f17, f27, f13
  649. LFD f24, 12 * SIZE(BO)
  650. LFD f25, 13 * SIZE(BO)
  651. LFD f26, 14 * SIZE(BO)
  652. LFD f27, 15 * SIZE(BO)
  653. fmadd f0, f18, f20, f0
  654. fmadd f4, f18, f21, f4
  655. fmadd f8, f18, f22, f8
  656. fmadd f12, f18, f23, f12
  657. LFD f20, 16 * SIZE(BO)
  658. LFD f21, 17 * SIZE(BO)
  659. LFD f22, 18 * SIZE(BO)
  660. LFD f23, 19 * SIZE(BO)
  661. fmadd f1, f19, f24, f1
  662. fmadd f5, f19, f25, f5
  663. fmadd f9, f19, f26, f9
  664. fmadd f13, f19, f27, f13
  665. LFD f16, 4 * SIZE(AO)
  666. LFD f17, 5 * SIZE(AO)
  667. LFD f18, 6 * SIZE(AO)
  668. LFD f19, 7 * SIZE(AO)
  669. LFD f24, 20 * SIZE(BO)
  670. LFD f25, 21 * SIZE(BO)
  671. LFD f26, 22 * SIZE(BO)
  672. LFD f27, 23 * SIZE(BO)
  673. addi AO, AO, 4 * SIZE
  674. addi BO, BO, 16 * SIZE
  675. DCBT(BO, PREB)
  676. bdnz LL(32)
  677. fadd f0, f1, f0
  678. fadd f4, f5, f4
  679. fadd f8, f9, f8
  680. fadd f12, f13, f12
  681. .align 4
  682. LL(35):
  683. lfd f30, ALPHA
  684. andi. r0, K, 3
  685. mtspr CTR, r0
  686. ble+ LL(38)
  687. .align 4
  688. LL(36):
  689. fmadd f0, f16, f20, f0
  690. fmadd f4, f16, f21, f4
  691. fmadd f8, f16, f22, f8
  692. fmadd f12, f16, f23, f12
  693. LFD f16, 1 * SIZE(AO)
  694. LFD f20, 4 * SIZE(BO)
  695. LFD f21, 5 * SIZE(BO)
  696. LFD f22, 6 * SIZE(BO)
  697. LFD f23, 7 * SIZE(BO)
  698. addi BO, BO, 4 * SIZE
  699. addi AO, AO, 1 * SIZE
  700. bdnz LL(36)
  701. .align 4
  702. LL(38):
  703. LFD f16, 0 * SIZE(CO1)
  704. LFD f18, 0 * SIZE(CO2)
  705. LFD f20, 0 * SIZE(CO3)
  706. LFD f22, 0 * SIZE(CO4)
  707. fmadd f0, f0, f30, f16
  708. fmadd f4, f4, f30, f18
  709. fmadd f8, f8, f30, f20
  710. fmadd f12, f12, f30, f22
  711. STFD f0, 0 * SIZE(CO1)
  712. STFD f4, 0 * SIZE(CO2)
  713. STFD f8, 0 * SIZE(CO3)
  714. STFD f12, 0 * SIZE(CO4)
  715. lfs f0, FZERO
  716. fmr f1, f0
  717. fmr f4, f0
  718. fmr f5, f0
  719. fmr f8, f0
  720. fmr f9, f0
  721. fmr f12, f0
  722. fmr f13, f0
  723. .align 4
  724. LL(39):
  725. mr B, BO
  726. addic. J, J, -1
  727. lfs f0, FZERO
  728. bgt LL(10)
  729. .align 4
  730. LL(40):
  731. mr CO1, C
  732. add CO2, C, LDC
  733. andi. J, N, 2
  734. ble LL(70)
  735. fmr f1, f0
  736. fmr f2, f0
  737. fmr f3, f0
  738. fmr f4, f0
  739. fmr f5, f0
  740. fmr f6, f0
  741. fmr f7, f0
  742. srawi. I, M, 2
  743. add C, CO2, LDC
  744. mr AO, A
  745. ble LL(50)
  746. .align 4
  747. LL(41):
  748. LFD f16, 0 * SIZE(AO)
  749. LFD f17, 1 * SIZE(AO)
  750. LFD f18, 2 * SIZE(AO)
  751. LFD f19, 3 * SIZE(AO)
  752. LFD f20, 0 * SIZE(B)
  753. LFD f21, 1 * SIZE(B)
  754. LFD f22, 2 * SIZE(B)
  755. LFD f23, 3 * SIZE(B)
  756. PREFETCH_C1
  757. PREFETCH_C2
  758. srawi. r0, K, 2
  759. mtspr CTR, r0
  760. mr BO, B
  761. ble LL(45)
  762. .align 5
  763. LL(42):
  764. fmadd f0, f16, f20, f0
  765. fmadd f1, f17, f20, f1
  766. fmadd f2, f18, f20, f2
  767. fmadd f3, f19, f20, f3
  768. fmadd f4, f16, f21, f4
  769. fmadd f5, f17, f21, f5
  770. fmadd f6, f18, f21, f6
  771. fmadd f7, f19, f21, f7
  772. LFD f16, 4 * SIZE(AO)
  773. LFD f17, 5 * SIZE(AO)
  774. LFD f18, 6 * SIZE(AO)
  775. LFD f19, 7 * SIZE(AO)
  776. fmadd f0, f16, f22, f0
  777. fmadd f1, f17, f22, f1
  778. fmadd f2, f18, f22, f2
  779. fmadd f3, f19, f22, f3
  780. fmadd f4, f16, f23, f4
  781. fmadd f5, f17, f23, f5
  782. fmadd f6, f18, f23, f6
  783. fmadd f7, f19, f23, f7
  784. LFD f16, 8 * SIZE(AO)
  785. LFD f17, 9 * SIZE(AO)
  786. LFD f18, 10 * SIZE(AO)
  787. LFD f19, 11 * SIZE(AO)
  788. LFD f20, 4 * SIZE(BO)
  789. LFD f21, 5 * SIZE(BO)
  790. LFD f22, 6 * SIZE(BO)
  791. LFD f23, 7 * SIZE(BO)
  792. fmadd f0, f16, f20, f0
  793. fmadd f1, f17, f20, f1
  794. fmadd f2, f18, f20, f2
  795. fmadd f3, f19, f20, f3
  796. fmadd f4, f16, f21, f4
  797. fmadd f5, f17, f21, f5
  798. fmadd f6, f18, f21, f6
  799. fmadd f7, f19, f21, f7
  800. LFD f16, 12 * SIZE(AO)
  801. LFD f17, 13 * SIZE(AO)
  802. LFD f18, 14 * SIZE(AO)
  803. LFD f19, 15 * SIZE(AO)
  804. fmadd f0, f16, f22, f0
  805. fmadd f1, f17, f22, f1
  806. fmadd f2, f18, f22, f2
  807. fmadd f3, f19, f22, f3
  808. fmadd f4, f16, f23, f4
  809. fmadd f5, f17, f23, f5
  810. fmadd f6, f18, f23, f6
  811. fmadd f7, f19, f23, f7
  812. LFD f16, 16 * SIZE(AO)
  813. LFD f17, 17 * SIZE(AO)
  814. LFD f18, 18 * SIZE(AO)
  815. LFD f19, 19 * SIZE(AO)
  816. LFD f20, 8 * SIZE(BO)
  817. LFD f21, 9 * SIZE(BO)
  818. LFD f22, 10 * SIZE(BO)
  819. LFD f23, 11 * SIZE(BO)
  820. addi AO, AO, 16 * SIZE
  821. addi BO, BO, 8 * SIZE
  822. DCBT(BO, PREB)
  823. bdnz LL(42)
  824. .align 4
  825. LL(45):
  826. lfd f30, ALPHA
  827. andi. r0, K, 3
  828. mtspr CTR, r0
  829. ble+ LL(48)
  830. .align 4
  831. LL(46):
  832. fmadd f0, f16, f20, f0
  833. fmadd f1, f17, f20, f1
  834. fmadd f2, f18, f20, f2
  835. fmadd f3, f19, f20, f3
  836. fmadd f4, f16, f21, f4
  837. fmadd f5, f17, f21, f5
  838. fmadd f6, f18, f21, f6
  839. fmadd f7, f19, f21, f7
  840. LFD f16, 4 * SIZE(AO)
  841. LFD f17, 5 * SIZE(AO)
  842. LFD f18, 6 * SIZE(AO)
  843. LFD f19, 7 * SIZE(AO)
  844. LFD f20, 2 * SIZE(BO)
  845. LFD f21, 3 * SIZE(BO)
  846. addi BO, BO, 2 * SIZE
  847. addi AO, AO, 4 * SIZE
  848. bdnz LL(46)
  849. .align 4
  850. LL(48):
  851. LFD f16, 0 * SIZE(CO1)
  852. LFD f17, 1 * SIZE(CO1)
  853. LFD f18, 2 * SIZE(CO1)
  854. LFD f19, 3 * SIZE(CO1)
  855. LFD f20, 0 * SIZE(CO2)
  856. LFD f21, 1 * SIZE(CO2)
  857. LFD f22, 2 * SIZE(CO2)
  858. LFD f23, 3 * SIZE(CO2)
  859. fmadd f0, f0, f30, f16
  860. fmadd f1, f1, f30, f17
  861. fmadd f2, f2, f30, f18
  862. fmadd f3, f3, f30, f19
  863. fmadd f4, f4, f30, f20
  864. fmadd f5, f5, f30, f21
  865. fmadd f6, f6, f30, f22
  866. fmadd f7, f7, f30, f23
  867. STFD f0, 0 * SIZE(CO1)
  868. STFD f1, 1 * SIZE(CO1)
  869. STFD f2, 2 * SIZE(CO1)
  870. STFD f3, 3 * SIZE(CO1)
  871. lfs f0, FZERO
  872. fmr f1, f0
  873. fmr f2, f0
  874. fmr f3, f0
  875. STFD f4, 0 * SIZE(CO2)
  876. STFD f5, 1 * SIZE(CO2)
  877. STFD f6, 2 * SIZE(CO2)
  878. STFD f7, 3 * SIZE(CO2)
  879. fmr f4, f0
  880. fmr f5, f0
  881. fmr f6, f0
  882. fmr f7, f0
  883. addi CO1, CO1, 4 * SIZE
  884. addi CO2, CO2, 4 * SIZE
  885. addic. I, I, -1
  886. bgt+ LL(41)
  887. .align 4
  888. LL(50):
  889. andi. I, M, 2
  890. ble LL(60)
  891. LFD f16, 0 * SIZE(AO)
  892. LFD f17, 1 * SIZE(AO)
  893. LFD f18, 2 * SIZE(AO)
  894. LFD f19, 3 * SIZE(AO)
  895. LFD f20, 0 * SIZE(B)
  896. LFD f21, 1 * SIZE(B)
  897. LFD f22, 2 * SIZE(B)
  898. LFD f23, 3 * SIZE(B)
  899. LFD f24, 4 * SIZE(B)
  900. LFD f25, 5 * SIZE(B)
  901. LFD f26, 6 * SIZE(B)
  902. LFD f27, 7 * SIZE(B)
  903. srawi. r0, K, 2
  904. mtspr CTR, r0
  905. mr BO, B
  906. ble LL(55)
  907. .align 5
  908. LL(52):
  909. fmadd f0, f16, f20, f0
  910. fmadd f1, f17, f20, f1
  911. fmadd f2, f16, f21, f2
  912. fmadd f3, f17, f21, f3
  913. fmadd f4, f18, f22, f4
  914. fmadd f5, f19, f22, f5
  915. fmadd f6, f18, f23, f6
  916. fmadd f7, f19, f23, f7
  917. LFD f16, 4 * SIZE(AO)
  918. LFD f17, 5 * SIZE(AO)
  919. LFD f18, 6 * SIZE(AO)
  920. LFD f19, 7 * SIZE(AO)
  921. LFD f20, 8 * SIZE(BO)
  922. LFD f21, 9 * SIZE(BO)
  923. LFD f22, 10 * SIZE(BO)
  924. LFD f23, 11 * SIZE(BO)
  925. fmadd f0, f16, f24, f0
  926. fmadd f1, f17, f24, f1
  927. fmadd f2, f16, f25, f2
  928. fmadd f3, f17, f25, f3
  929. fmadd f4, f18, f26, f4
  930. fmadd f5, f19, f26, f5
  931. fmadd f6, f18, f27, f6
  932. fmadd f7, f19, f27, f7
  933. LFD f16, 8 * SIZE(AO)
  934. LFD f17, 9 * SIZE(AO)
  935. LFD f18, 10 * SIZE(AO)
  936. LFD f19, 11 * SIZE(AO)
  937. LFD f24, 12 * SIZE(BO)
  938. LFD f25, 13 * SIZE(BO)
  939. LFD f26, 14 * SIZE(BO)
  940. LFD f27, 15 * SIZE(BO)
  941. addi AO, AO, 8 * SIZE
  942. addi BO, BO, 8 * SIZE
  943. DCBT(BO, PREB)
  944. bdnz LL(52)
  945. .align 4
  946. LL(55):
  947. lfd f30, ALPHA
  948. andi. r0, K, 3
  949. mtspr CTR, r0
  950. ble+ LL(58)
  951. .align 4
  952. LL(56):
  953. fmadd f0, f16, f20, f0
  954. fmadd f1, f17, f20, f1
  955. fmadd f2, f16, f21, f2
  956. fmadd f3, f17, f21, f3
  957. LFD f16, 2 * SIZE(AO)
  958. LFD f17, 3 * SIZE(AO)
  959. LFD f20, 2 * SIZE(BO)
  960. LFD f21, 3 * SIZE(BO)
  961. addi BO, BO, 2 * SIZE
  962. addi AO, AO, 2 * SIZE
  963. bdnz LL(56)
  964. .align 4
  965. LL(58):
  966. LFD f16, 0 * SIZE(CO1)
  967. LFD f17, 1 * SIZE(CO1)
  968. LFD f18, 0 * SIZE(CO2)
  969. LFD f19, 1 * SIZE(CO2)
  970. fadd f0, f4, f0
  971. fadd f1, f5, f1
  972. fadd f2, f6, f2
  973. fadd f3, f7, f3
  974. fmadd f0, f0, f30, f16
  975. fmadd f1, f1, f30, f17
  976. fmadd f2, f2, f30, f18
  977. fmadd f3, f3, f30, f19
  978. STFD f0, 0 * SIZE(CO1)
  979. STFD f1, 1 * SIZE(CO1)
  980. STFD f2, 0 * SIZE(CO2)
  981. STFD f3, 1 * SIZE(CO2)
  982. lfs f0, FZERO
  983. fmr f1, f0
  984. fmr f2, f0
  985. fmr f3, f0
  986. fmr f4, f0
  987. fmr f5, f0
  988. fmr f6, f0
  989. fmr f7, f0
  990. addi CO1, CO1, 2 * SIZE
  991. addi CO2, CO2, 2 * SIZE
  992. .align 4
  993. LL(60):
  994. andi. I, M, 1
  995. ble LL(69)
  996. LFD f16, 0 * SIZE(AO)
  997. LFD f17, 1 * SIZE(AO)
  998. LFD f18, 2 * SIZE(AO)
  999. LFD f19, 3 * SIZE(AO)
  1000. LFD f20, 0 * SIZE(B)
  1001. LFD f21, 1 * SIZE(B)
  1002. LFD f22, 2 * SIZE(B)
  1003. LFD f23, 3 * SIZE(B)
  1004. LFD f24, 4 * SIZE(B)
  1005. LFD f25, 5 * SIZE(B)
  1006. LFD f26, 6 * SIZE(B)
  1007. LFD f27, 7 * SIZE(B)
  1008. srawi. r0, K, 2
  1009. mtspr CTR, r0
  1010. mr BO, B
  1011. ble LL(65)
  1012. .align 5
  1013. LL(62):
  1014. fmadd f0, f16, f20, f0
  1015. fmadd f1, f16, f21, f1
  1016. fmadd f2, f17, f22, f2
  1017. fmadd f3, f17, f23, f3
  1018. LFD f20, 8 * SIZE(BO)
  1019. LFD f21, 9 * SIZE(BO)
  1020. LFD f22, 10 * SIZE(BO)
  1021. LFD f23, 11 * SIZE(BO)
  1022. fmadd f0, f18, f24, f0
  1023. fmadd f1, f18, f25, f1
  1024. fmadd f2, f19, f26, f2
  1025. fmadd f3, f19, f27, f3
  1026. LFD f16, 4 * SIZE(AO)
  1027. LFD f17, 5 * SIZE(AO)
  1028. LFD f18, 6 * SIZE(AO)
  1029. LFD f19, 7 * SIZE(AO)
  1030. LFD f24, 12 * SIZE(BO)
  1031. LFD f25, 13 * SIZE(BO)
  1032. LFD f26, 14 * SIZE(BO)
  1033. LFD f27, 15 * SIZE(BO)
  1034. addi AO, AO, 4 * SIZE
  1035. addi BO, BO, 8 * SIZE
  1036. bdnz LL(62)
  1037. .align 4
  1038. LL(65):
  1039. lfd f30, ALPHA
  1040. andi. r0, K, 3
  1041. mtspr CTR, r0
  1042. ble+ LL(68)
  1043. .align 4
  1044. LL(66):
  1045. fmadd f0, f16, f20, f0
  1046. fmadd f1, f16, f21, f1
  1047. LFD f16, 1 * SIZE(AO)
  1048. LFD f20, 2 * SIZE(BO)
  1049. LFD f21, 3 * SIZE(BO)
  1050. addi BO, BO, 2 * SIZE
  1051. addi AO, AO, 1 * SIZE
  1052. bdnz LL(66)
  1053. .align 4
  1054. LL(68):
  1055. LFD f16, 0 * SIZE(CO1)
  1056. LFD f18, 0 * SIZE(CO2)
  1057. fadd f0, f2, f0
  1058. fadd f1, f3, f1
  1059. fmadd f0, f0, f30, f16
  1060. fmadd f1, f1, f30, f18
  1061. STFD f0, 0 * SIZE(CO1)
  1062. STFD f1, 0 * SIZE(CO2)
  1063. lfs f0, FZERO
  1064. fmr f1, f0
  1065. fmr f4, f0
  1066. fmr f5, f0
  1067. .align 4
  1068. LL(69):
  1069. mr B, BO
  1070. lfs f0, FZERO
  1071. .align 4
  1072. LL(70):
  1073. mr CO1, C
  1074. andi. J, N, 1
  1075. ble LL(999)
  1076. fmr f1, f0
  1077. fmr f2, f0
  1078. fmr f3, f0
  1079. srawi. I, M, 2
  1080. mr AO, A
  1081. ble LL(80)
  1082. .align 4
  1083. LL(71):
  1084. LFD f16, 0 * SIZE(AO)
  1085. LFD f17, 1 * SIZE(AO)
  1086. LFD f18, 2 * SIZE(AO)
  1087. LFD f19, 3 * SIZE(AO)
  1088. LFD f20, 0 * SIZE(B)
  1089. LFD f21, 1 * SIZE(B)
  1090. LFD f22, 2 * SIZE(B)
  1091. LFD f23, 3 * SIZE(B)
  1092. PREFETCH_C1
  1093. srawi. r0, K, 2
  1094. mtspr CTR, r0
  1095. mr BO, B
  1096. ble LL(75)
  1097. .align 5
  1098. LL(72):
  1099. fmadd f0, f16, f20, f0
  1100. fmadd f1, f17, f20, f1
  1101. fmadd f2, f18, f20, f2
  1102. fmadd f3, f19, f20, f3
  1103. LFD f16, 4 * SIZE(AO)
  1104. LFD f17, 5 * SIZE(AO)
  1105. LFD f18, 6 * SIZE(AO)
  1106. LFD f19, 7 * SIZE(AO)
  1107. fmadd f0, f16, f21, f0
  1108. fmadd f1, f17, f21, f1
  1109. fmadd f2, f18, f21, f2
  1110. fmadd f3, f19, f21, f3
  1111. LFD f16, 8 * SIZE(AO)
  1112. LFD f17, 9 * SIZE(AO)
  1113. LFD f18, 10 * SIZE(AO)
  1114. LFD f19, 11 * SIZE(AO)
  1115. fmadd f0, f16, f22, f0
  1116. fmadd f1, f17, f22, f1
  1117. fmadd f2, f18, f22, f2
  1118. fmadd f3, f19, f22, f3
  1119. LFD f16, 12 * SIZE(AO)
  1120. LFD f17, 13 * SIZE(AO)
  1121. LFD f18, 14 * SIZE(AO)
  1122. LFD f19, 15 * SIZE(AO)
  1123. fmadd f0, f16, f23, f0
  1124. fmadd f1, f17, f23, f1
  1125. fmadd f2, f18, f23, f2
  1126. fmadd f3, f19, f23, f3
  1127. LFD f16, 16 * SIZE(AO)
  1128. LFD f17, 17 * SIZE(AO)
  1129. LFD f18, 18 * SIZE(AO)
  1130. LFD f19, 19 * SIZE(AO)
  1131. LFD f20, 4 * SIZE(BO)
  1132. LFD f21, 5 * SIZE(BO)
  1133. LFD f22, 6 * SIZE(BO)
  1134. LFD f23, 7 * SIZE(BO)
  1135. addi AO, AO, 16 * SIZE
  1136. addi BO, BO, 4 * SIZE
  1137. DCBT(BO, PREB)
  1138. bdnz LL(72)
  1139. .align 4
  1140. LL(75):
  1141. lfd f30, ALPHA
  1142. andi. r0, K, 3
  1143. mtspr CTR, r0
  1144. ble+ LL(78)
  1145. .align 4
  1146. LL(76):
  1147. fmadd f0, f16, f20, f0
  1148. fmadd f1, f17, f20, f1
  1149. fmadd f2, f18, f20, f2
  1150. fmadd f3, f19, f20, f3
  1151. LFD f16, 4 * SIZE(AO)
  1152. LFD f17, 5 * SIZE(AO)
  1153. LFD f18, 6 * SIZE(AO)
  1154. LFD f19, 7 * SIZE(AO)
  1155. LFD f20, 1 * SIZE(BO)
  1156. addi BO, BO, 1 * SIZE
  1157. addi AO, AO, 4 * SIZE
  1158. bdnz LL(76)
  1159. .align 4
  1160. LL(78):
  1161. LFD f16, 0 * SIZE(CO1)
  1162. LFD f17, 1 * SIZE(CO1)
  1163. LFD f18, 2 * SIZE(CO1)
  1164. LFD f19, 3 * SIZE(CO1)
  1165. fmadd f0, f0, f30, f16
  1166. fmadd f1, f1, f30, f17
  1167. fmadd f2, f2, f30, f18
  1168. fmadd f3, f3, f30, f19
  1169. STFD f0, 0 * SIZE(CO1)
  1170. STFD f1, 1 * SIZE(CO1)
  1171. STFD f2, 2 * SIZE(CO1)
  1172. STFD f3, 3 * SIZE(CO1)
  1173. lfs f0, FZERO
  1174. fmr f1, f0
  1175. fmr f2, f0
  1176. fmr f3, f0
  1177. addi CO1, CO1, 4 * SIZE
  1178. addic. I, I, -1
  1179. bgt+ LL(71)
  1180. .align 4
  1181. LL(80):
  1182. andi. I, M, 2
  1183. ble LL(90)
  1184. LFD f16, 0 * SIZE(AO)
  1185. LFD f17, 1 * SIZE(AO)
  1186. LFD f18, 2 * SIZE(AO)
  1187. LFD f19, 3 * SIZE(AO)
  1188. LFD f20, 0 * SIZE(B)
  1189. LFD f21, 1 * SIZE(B)
  1190. LFD f22, 2 * SIZE(B)
  1191. LFD f23, 3 * SIZE(B)
  1192. srawi. r0, K, 2
  1193. mtspr CTR, r0
  1194. mr BO, B
  1195. ble LL(85)
  1196. .align 5
  1197. LL(82):
  1198. fmadd f0, f16, f20, f0
  1199. fmadd f1, f17, f20, f1
  1200. fmadd f2, f18, f21, f2
  1201. fmadd f3, f19, f21, f3
  1202. LFD f16, 4 * SIZE(AO)
  1203. LFD f17, 5 * SIZE(AO)
  1204. LFD f18, 6 * SIZE(AO)
  1205. LFD f19, 7 * SIZE(AO)
  1206. fmadd f0, f16, f22, f0
  1207. fmadd f1, f17, f22, f1
  1208. fmadd f2, f18, f23, f2
  1209. fmadd f3, f19, f23, f3
  1210. LFD f16, 8 * SIZE(AO)
  1211. LFD f17, 9 * SIZE(AO)
  1212. LFD f18, 10 * SIZE(AO)
  1213. LFD f19, 11 * SIZE(AO)
  1214. LFD f20, 4 * SIZE(BO)
  1215. LFD f21, 5 * SIZE(BO)
  1216. LFD f22, 6 * SIZE(BO)
  1217. LFD f23, 7 * SIZE(BO)
  1218. addi AO, AO, 8 * SIZE
  1219. addi BO, BO, 4 * SIZE
  1220. DCBT(BO, PREB)
  1221. bdnz LL(82)
  1222. .align 4
  1223. LL(85):
  1224. lfd f30, ALPHA
  1225. andi. r0, K, 3
  1226. mtspr CTR, r0
  1227. ble+ LL(88)
  1228. .align 4
  1229. LL(86):
  1230. fmadd f0, f16, f20, f0
  1231. fmadd f1, f17, f20, f1
  1232. LFD f16, 2 * SIZE(AO)
  1233. LFD f17, 3 * SIZE(AO)
  1234. LFD f20, 1 * SIZE(BO)
  1235. addi BO, BO, 1 * SIZE
  1236. addi AO, AO, 2 * SIZE
  1237. bdnz LL(86)
  1238. .align 4
  1239. LL(88):
  1240. LFD f16, 0 * SIZE(CO1)
  1241. LFD f17, 1 * SIZE(CO1)
  1242. fadd f0, f2, f0
  1243. fadd f1, f3, f1
  1244. fmadd f0, f0, f30, f16
  1245. fmadd f1, f1, f30, f17
  1246. STFD f0, 0 * SIZE(CO1)
  1247. STFD f1, 1 * SIZE(CO1)
  1248. addi CO1, CO1, 2 * SIZE
  1249. lfs f0, FZERO
  1250. fmr f1, f0
  1251. fmr f2, f0
  1252. fmr f3, f0
  1253. .align 4
  1254. LL(90):
  1255. andi. I, M, 1
  1256. ble LL(999)
  1257. LFD f16, 0 * SIZE(AO)
  1258. LFD f17, 1 * SIZE(AO)
  1259. LFD f18, 2 * SIZE(AO)
  1260. LFD f19, 3 * SIZE(AO)
  1261. LFD f20, 0 * SIZE(B)
  1262. LFD f21, 1 * SIZE(B)
  1263. LFD f22, 2 * SIZE(B)
  1264. LFD f23, 3 * SIZE(B)
  1265. srawi. r0, K, 3
  1266. mtspr CTR, r0
  1267. mr BO, B
  1268. ble LL(95)
  1269. .align 5
  1270. LL(92):
  1271. fmadd f0, f16, f20, f0
  1272. fmadd f1, f17, f21, f1
  1273. fmadd f2, f18, f22, f2
  1274. fmadd f3, f19, f23, f3
  1275. LFD f16, 4 * SIZE(AO)
  1276. LFD f17, 5 * SIZE(AO)
  1277. LFD f18, 6 * SIZE(AO)
  1278. LFD f19, 7 * SIZE(AO)
  1279. LFD f20, 4 * SIZE(BO)
  1280. LFD f21, 5 * SIZE(BO)
  1281. LFD f22, 6 * SIZE(BO)
  1282. LFD f23, 7 * SIZE(BO)
  1283. fmadd f0, f16, f20, f0
  1284. fmadd f1, f17, f21, f1
  1285. fmadd f2, f18, f22, f2
  1286. fmadd f3, f19, f23, f3
  1287. LFD f16, 8 * SIZE(AO)
  1288. LFD f17, 9 * SIZE(AO)
  1289. LFD f18, 10 * SIZE(AO)
  1290. LFD f19, 11 * SIZE(AO)
  1291. LFD f20, 8 * SIZE(BO)
  1292. LFD f21, 9 * SIZE(BO)
  1293. LFD f22, 10 * SIZE(BO)
  1294. LFD f23, 11 * SIZE(BO)
  1295. addi AO, AO, 8 * SIZE
  1296. addi BO, BO, 8 * SIZE
  1297. bdnz LL(92)
  1298. .align 4
  1299. LL(95):
  1300. lfd f30, ALPHA
  1301. andi. r0, K, 7
  1302. mtspr CTR, r0
  1303. ble+ LL(98)
  1304. .align 4
  1305. LL(96):
  1306. fmadd f0, f16, f20, f0
  1307. LFD f16, 1 * SIZE(AO)
  1308. LFD f20, 1 * SIZE(BO)
  1309. addi BO, BO, 1 * SIZE
  1310. addi AO, AO, 1 * SIZE
  1311. bdnz LL(96)
  1312. .align 4
  1313. LL(98):
  1314. LFD f16, 0 * SIZE(CO1)
  1315. fadd f0, f1, f0
  1316. fadd f2, f3, f2
  1317. fadd f0, f2, f0
  1318. fmadd f0, f0, f30, f16
  1319. STFD f0, 0 * SIZE(CO1)
  1320. .align 4
  1321. LL(999):
  1322. addi r3, 0, 0
  1323. lfd f14, 0(SP)
  1324. lfd f15, 8(SP)
  1325. lfd f16, 16(SP)
  1326. lfd f17, 24(SP)
  1327. lfd f18, 32(SP)
  1328. lfd f19, 40(SP)
  1329. lfd f20, 48(SP)
  1330. lfd f21, 56(SP)
  1331. lfd f22, 64(SP)
  1332. lfd f23, 72(SP)
  1333. lfd f24, 80(SP)
  1334. lfd f25, 88(SP)
  1335. lfd f26, 96(SP)
  1336. lfd f27, 104(SP)
  1337. lfd f28, 112(SP)
  1338. lfd f29, 120(SP)
  1339. lfd f30, 128(SP)
  1340. lfd f31, 136(SP)
  1341. #ifdef __64BIT__
  1342. ld r31, 144(SP)
  1343. ld r30, 152(SP)
  1344. ld r29, 160(SP)
  1345. ld r28, 168(SP)
  1346. ld r27, 176(SP)
  1347. ld r26, 184(SP)
  1348. ld r25, 192(SP)
  1349. ld r24, 200(SP)
  1350. ld r23, 208(SP)
  1351. ld r22, 216(SP)
  1352. ld r21, 224(SP)
  1353. #else
  1354. lwz r31, 144(SP)
  1355. lwz r30, 148(SP)
  1356. lwz r29, 152(SP)
  1357. lwz r28, 156(SP)
  1358. lwz r27, 160(SP)
  1359. lwz r26, 164(SP)
  1360. lwz r25, 168(SP)
  1361. lwz r24, 172(SP)
  1362. lwz r23, 176(SP)
  1363. lwz r22, 180(SP)
  1364. lwz r21, 184(SP)
  1365. #endif
  1366. addi SP, SP, STACKSIZE
  1367. blr
  1368. EPILOGUE
  1369. #endif