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OpenBLAS/TargetList.txt

TargetList.txt 793 B
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Added docs for make TARGET=your_cpu_target.
15 years ago
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TargetList.txt: minor re-ordering
13 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Init Sandybridge codes based on Nehalem.
14 years ago
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
11 years ago
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
7 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Refs #113. Fixed the typo BOBCATE -> BOBCAT
13 years ago
Added BULLDOZER target. So far it uses barcelona kernels.
13 years ago
Update the doc for target list.
11 years ago
added target processor STEAMROLLER
11 years ago
Add AMD Excavator target.
10 years ago
Add ZEN support (tested for auto-detected static backend)
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Add POWER7/POWER8 as targets
10 years ago
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Added docs for make TARGET=your_cpu_target.
15 years ago
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MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Add MIPS 1004K target
7 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Added docs for make TARGET=your_cpu_target.
15 years ago
​
Init Sandybridge codes based on Nehalem.
14 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added mips I6500 core Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
8 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
​
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
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Update the doc for target list.
11 years ago
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Add ARM targets.
11 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
ARM64: Add the VULCAN Target
9 years ago
ARM64: Add Cavium THUNDERX Target
9 years ago
ARM64: Add Cavium THUNDERX2T99 Target
9 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
Add support for TARGET=ZARCH_GENERIC and TARGET=Z13
8 years ago
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  1. Force Target Examples:

  2. 

  3. make TARGET=NEHALEM

  4. make TARGET=LOONGSON3A BINARY=64

  5. make TARGET=ISTANBUL

  6. 

  7. Supported List:

  8. 1.X86/X86_64

  9. a)Intel CPU:

  10. P2

  11. KATMAI

  12. COPPERMINE

  13. NORTHWOOD

  14. PRESCOTT

  15. BANIAS

  16. YONAH

  17. CORE2

  18. PENRYN

  19. DUNNINGTON

  20. NEHALEM

  21. SANDYBRIDGE

  22. HASWELL

  23. SKYLAKEX

  24. ATOM

  25. 

  26. b)AMD CPU:

  27. ATHLON

  28. OPTERON

  29. OPTERON_SSE3

  30. BARCELONA

  31. SHANGHAI

  32. ISTANBUL

  33. BOBCAT

  34. BULLDOZER

  35. PILEDRIVER

  36. STEAMROLLER

  37. EXCAVATOR

  38. ZEN

  39. 

  40. c)VIA CPU:

  41. SSE_GENERIC

  42. VIAC3

  43. NANO

  44. 

  45. 2.Power CPU:

  46. POWER4

  47. POWER5

  48. POWER6

  49. POWER7

  50. POWER8

  51. PPCG4

  52. PPC970

  53. PPC970MP

  54. PPC440

  55. PPC440FP2

  56. CELL

  57. 

  58. 3.MIPS CPU:

  59. P5600

  60. 1004K

  61. 

  62. 4.MIPS64 CPU:

  63. SICORTEX

  64. LOONGSON3A

  65. LOONGSON3B

  66. I6400

  67. P6600

  68. I6500

  69. 

  70. 5.IA64 CPU:

  71. ITANIUM2

  72. 

  73. 6.SPARC CPU:

  74. SPARC

  75. SPARCV7

  76. 

  77. 7.ARM CPU:

  78. CORTEXA15

  79. CORTEXA9

  80. ARMV7

  81. ARMV6

  82. ARMV5

  83. 

  84. 8.ARM 64-bit CPU:

  85. ARMV8

  86. CORTEXA57

  87. VULCAN

  88. THUNDERX

  89. THUNDERX2T99

  90. 

  91. 9.System Z:

  92. ZARCH_GENERIC

  93. Z13

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.