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OpenBLAS/TargetList.txt

TargetList.txt 742 B
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Added docs for make TARGET=your_cpu_target.
15 years ago
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TargetList.txt: minor re-ordering
13 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Init Sandybridge codes based on Nehalem.
14 years ago
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
11 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Refs #113. Fixed the typo BOBCATE -> BOBCAT
13 years ago
Added BULLDOZER target. So far it uses barcelona kernels.
13 years ago
Update the doc for target list.
11 years ago
added target processor STEAMROLLER
11 years ago
Add AMD Excavator target.
10 years ago
Add ZEN support (tested for auto-detected static backend)
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
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Add POWER7/POWER8 as targets
10 years ago
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Added docs for make TARGET=your_cpu_target.
15 years ago
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MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Added docs for make TARGET=your_cpu_target.
15 years ago
​
Init Sandybridge codes based on Nehalem.
14 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
15 years ago
​
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
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Update the doc for target list.
11 years ago
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Add ARM targets.
11 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
11 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
ARM64: Add the VULCAN Target
9 years ago
ARM64: Add Cavium THUNDERX Target
9 years ago
ARM64: Add Cavium THUNDERX2T99 Target
9 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
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  1. Force Target Examples:

  2. 

  3. make TARGET=NEHALEM

  4. make TARGET=LOONGSON3A BINARY=64

  5. make TARGET=ISTANBUL

  6. 

  7. Supported List:

  8. 1.X86/X86_64

  9. a)Intel CPU:

  10. P2

  11. KATMAI

  12. COPPERMINE

  13. NORTHWOOD

  14. PRESCOTT

  15. BANIAS

  16. YONAH

  17. CORE2

  18. PENRYN

  19. DUNNINGTON

  20. NEHALEM

  21. SANDYBRIDGE

  22. HASWELL

  23. ATOM

  24. 

  25. b)AMD CPU:

  26. ATHLON

  27. OPTERON

  28. OPTERON_SSE3

  29. BARCELONA

  30. SHANGHAI

  31. ISTANBUL

  32. BOBCAT

  33. BULLDOZER

  34. PILEDRIVER

  35. STEAMROLLER

  36. EXCAVATOR

  37. ZEN

  38. 

  39. c)VIA CPU:

  40. SSE_GENERIC

  41. VIAC3

  42. NANO

  43. 

  44. 2.Power CPU:

  45. POWER4

  46. POWER5

  47. POWER6

  48. POWER7

  49. POWER8

  50. PPCG4

  51. PPC970

  52. PPC970MP

  53. PPC440

  54. PPC440FP2

  55. CELL

  56. 

  57. 3.MIPS CPU:

  58. P5600

  59. 

  60. 4.MIPS64 CPU:

  61. SICORTEX

  62. LOONGSON3A

  63. LOONGSON3B

  64. I6400

  65. P6600

  66. 

  67. 5.IA64 CPU:

  68. ITANIUM2

  69. 

  70. 6.SPARC CPU:

  71. SPARC

  72. SPARCV7

  73. 

  74. 7.ARM CPU:

  75. CORTEXA15

  76. CORTEXA9

  77. ARMV7

  78. ARMV6

  79. ARMV5

  80. 

  81. 8.ARM 64-bit CPU:

  82. ARMV8

  83. CORTEXA57

  84. VULCAN

  85. THUNDERX

  86. THUNDERX2T99

  87.

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.