From e2c017121de2790c4ddcd385172326f46ed2f82c Mon Sep 17 00:00:00 2001 From: xutianchun Date: Thu, 18 Jun 2020 09:06:54 +0800 Subject: [PATCH] add MirrorPad op --- mindspore/ops/_op_impl/aicpu/__init__.py | 1 + mindspore/ops/_op_impl/aicpu/mirror_pad.py | 52 ++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 mindspore/ops/_op_impl/aicpu/mirror_pad.py diff --git a/mindspore/ops/_op_impl/aicpu/__init__.py b/mindspore/ops/_op_impl/aicpu/__init__.py index cf1d499a87..f514ac183e 100644 --- a/mindspore/ops/_op_impl/aicpu/__init__.py +++ b/mindspore/ops/_op_impl/aicpu/__init__.py @@ -32,3 +32,4 @@ from .reverse_sequence import _reverse_sequence_aicpu from .pack import _pack_aicpu from .crop_and_resize import _crop_and_resize_aicpu from .cast import _cast_aicpu +from .mirror_pad import _mirror_pad_aicpu diff --git a/mindspore/ops/_op_impl/aicpu/mirror_pad.py b/mindspore/ops/_op_impl/aicpu/mirror_pad.py new file mode 100644 index 0000000000..6f3855cc2d --- /dev/null +++ b/mindspore/ops/_op_impl/aicpu/mirror_pad.py @@ -0,0 +1,52 @@ +# Copyright 2020 Huawei Technologies Co., Ltd +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================ + +"""MirrorPad op""" +from mindspore.ops.op_info_register import op_info_register, AiCPURegOp, DataType +mirror_pad_op_info = AiCPURegOp("MirrorPad") \ + .fusion_type("OPAQUE") \ + .input(0, "x", "required") \ + .input(1, "paddings", "required") \ + .output(0, "y", "required") \ + .attr("mode", "str") \ + .dtype_format(DataType.I8_Default, DataType.I32_Default, DataType.I8_Default) \ + .dtype_format(DataType.I16_Default, DataType.I32_Default, DataType.I16_Default) \ + .dtype_format(DataType.I32_Default, DataType.I32_Default, DataType.I32_Default) \ + .dtype_format(DataType.I64_Default, DataType.I32_Default, DataType.I64_Default) \ + .dtype_format(DataType.U8_Default, DataType.I32_Default, DataType.U8_Default) \ + .dtype_format(DataType.U16_Default, DataType.I32_Default, DataType.U16_Default) \ + .dtype_format(DataType.U32_Default, DataType.I32_Default, DataType.U32_Default) \ + .dtype_format(DataType.U64_Default, DataType.I32_Default, DataType.U64_Default) \ + .dtype_format(DataType.F16_Default, DataType.I32_Default, DataType.F16_Default) \ + .dtype_format(DataType.F32_Default, DataType.I32_Default, DataType.F32_Default) \ + .dtype_format(DataType.F64_Default, DataType.I32_Default, DataType.F64_Default) \ + .dtype_format(DataType.I8_Default, DataType.I64_Default, DataType.I8_Default) \ + .dtype_format(DataType.I16_Default, DataType.I64_Default, DataType.I16_Default) \ + .dtype_format(DataType.I32_Default, DataType.I64_Default, DataType.I32_Default) \ + .dtype_format(DataType.I64_Default, DataType.I64_Default, DataType.I64_Default) \ + .dtype_format(DataType.U8_Default, DataType.I64_Default, DataType.U8_Default) \ + .dtype_format(DataType.U16_Default, DataType.I64_Default, DataType.U16_Default) \ + .dtype_format(DataType.U32_Default, DataType.I64_Default, DataType.U32_Default) \ + .dtype_format(DataType.U64_Default, DataType.I64_Default, DataType.U64_Default) \ + .dtype_format(DataType.F16_Default, DataType.I64_Default, DataType.F16_Default) \ + .dtype_format(DataType.F32_Default, DataType.I64_Default, DataType.F32_Default) \ + .dtype_format(DataType.F64_Default, DataType.I64_Default, DataType.F64_Default) \ + .get_op_info() + + +@op_info_register(mirror_pad_op_info) +def _mirror_pad_aicpu(): + """MirrorPad AiCPU register""" + return