syc op_base act type with schema

mindspore/lite/nnacl/assembly/arm32/MatmulFp32.S

@@ -91,7 +91,7 @@ LoopCol:
 
         Activation:
             ldr lr, [sp]
-            cmp lr, #2
+            cmp lr, #3
             beq Relu6
             cmp lr, #1
             beq Relu

mindspore/lite/nnacl/assembly/arm32/MatmulFp32Opt.S

@@ -106,7 +106,7 @@ LoopRow:
 
         Activation:
             ldr lr, [sp]
-            cmp lr, #2
+            cmp lr, #3
             beq Relu6
             cmp lr, #1
             beq Relu

mindspore/lite/nnacl/assembly/arm64/MatmulFp32.S

@@ -171,7 +171,7 @@ Bias:
   fadd v31.4s, v31.4s, v1.4s
 
 Activation:
-  cmp w4, #2
+  cmp w4, #3
   beq Relu6
   cmp w4, #1
   beq Relu

mindspore/lite/nnacl/assembly/arm64/MatmulFp32Opt.S

@@ -159,7 +159,7 @@ LoopRow:
             fadd v31.4s, v31.4s, v1.4s
 
         Activation:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu6
             cmp x4, #1
             beq Relu
@@ -278,7 +278,7 @@ LoopRow:
             fadd v30.4s, v30.4s, v0.4s
 
         ActivationHalf:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu6Half
             cmp x4, #1
             beq ReluHalf
@@ -401,7 +401,7 @@ LoopRow8:
             fadd v23.4s, v23.4s, v1.4s
 
         Activation8:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu68
             cmp x4, #1
             beq Relu8
@@ -492,7 +492,7 @@ LoopRow8:
             fadd v22.4s, v22.4s, v0.4s
 
         ActivationHalf8:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu6Half8
             cmp x4, #1
             beq ReluHalf8
@@ -582,7 +582,7 @@ LoopRow4:
             fadd v15.4s, v15.4s, v1.4s
 
         Activation4:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu64
             cmp x4, #1
             beq Relu4
@@ -645,7 +645,7 @@ LoopRow4:
             fadd v14.4s, v14.4s, v0.4s
 
         ActivationHalf4:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu6Half4
             cmp x4, #1
             beq ReluHalf4

mindspore/lite/nnacl/assembly/arm64/PostFuncBiasReluC8.S

@@ -67,7 +67,7 @@ Loop8x8:
   fadd v14.4s, v14.4s, v16.4s
   fadd v15.4s, v15.4s, v17.4s
 
-  cmp w7, #2
+  cmp w7, #3
   beq Relu6_8x8
   cmp w7, #1
   beq Relu_8x8

mindspore/lite/nnacl/assembly/fp16/MatmulFp16.S

@@ -249,7 +249,7 @@ Bias:
   fadd v31.8h, v31.8h, v0.8h
 
 Activation:
-  cmp w4, #2
+  cmp w4, #3
   beq Relu6
   cmp w4, #1
   beq Relu

mindspore/lite/nnacl/assembly/fp16/MatmulFp16Opt.S

@@ -205,7 +205,7 @@ LoopRow16:
             fadd v31.8h, v31.8h, v0.8h
 
         Activation16:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu616
             cmp x4, #1
             beq Relu16
@@ -344,7 +344,7 @@ LoopRow8:
             fadd v23.8h, v23.8h, v0.8h
 
         Activation8:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu68
             cmp x4, #1
             beq Relu8
@@ -439,7 +439,7 @@ LoopRow4:
             fadd v19.8h, v19.8h, v0.8h
 
         Activation4:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu64
             cmp x4, #1
             beq Relu4
@@ -512,7 +512,7 @@ LoopRow2:
             fadd v17.8h, v17.8h, v0.8h
 
         Activation2:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu62
             cmp x4, #1
             beq Relu2
@@ -574,7 +574,7 @@ LoopRow:
             fadd v16.8h, v16.8h, v0.8h
 
         Activation:
-            cmp x4, #2
+            cmp x4, #3
             beq Relu6
             cmp x4, #1
             beq Relu

mindspore/lite/nnacl/fp16/deconv_fp16.c

@@ -44,7 +44,7 @@ void PostConvFuncFp16C8(const float16_t *c8_out_ptr, float16_t *out_ptr, const f
   size_t oc8div = output_channel - oc8mod;
   size_t stride_size = stride * sizeof(float16_t);
   size_t relu_type = is_relu ? 1 : 0;
-  relu_type = is_relu6 ? 2 : relu_type;
+  relu_type = is_relu6 ? 3 : relu_type;
   PostFuncBiasReluC8Fp16(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type);
   return;
 }

mindspore/lite/nnacl/fp32/common_func.c

@@ -49,7 +49,7 @@ void PostConvFuncFp32C8(const float *c8_out_ptr, float *out_ptr, const float *bi
   size_t oc8div = output_channel - oc8mod;
   size_t stride_size = stride * sizeof(float);
   size_t relu_type = is_relu ? 1 : 0;
-  relu_type = is_relu6 ? 2 : relu_type;
+  relu_type = is_relu6 ? 3 : relu_type;
   PostFuncBiasReluC8(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type);
 #endif
   return;

mindspore/lite/nnacl/op_base.h

@@ -68,6 +68,6 @@ typedef struct OpParameter {
   int thread_num_;
 } OpParameter;
 
-typedef enum ActType { ActType_No, ActType_Relu, ActType_Relu6, ActType_Prelu } ActType;
+typedef enum ActType { ActType_No, ActType_Relu, ActType_Sigmod, ActType_Relu6, ActType_Prelu } ActType;
 
 #endif  // MINDSPORE_LITE_NNACL_OP_BASE_H_