From 21ce520b80f4f25b0c1e17cf22070556c0b3ef7c Mon Sep 17 00:00:00 2001 From: wuxuejian Date: Tue, 12 Jan 2021 20:37:05 +0800 Subject: [PATCH] update aicpu op format --- .../ops/_op_impl/aicpu/ctc_greedy_decoder.py | 4 ---- mindspore/ops/_op_impl/aicpu/ctcloss.py | 4 ---- .../ops/_op_impl/aicpu/dropout_genmask.py | 2 +- mindspore/ops/_op_impl/aicpu/expand_dims.py | 12 ---------- mindspore/ops/_op_impl/aicpu/flatten.py | 10 -------- mindspore/ops/_op_impl/aicpu/gamma.py | 1 - mindspore/ops/_op_impl/aicpu/is_finite.py | 12 ---------- mindspore/ops/_op_impl/aicpu/poisson.py | 1 - .../_op_impl/aicpu/random_choice_with_mask.py | 1 - mindspore/ops/_op_impl/aicpu/reshape.py | 12 ---------- .../ops/_op_impl/aicpu/reverse_sequence.py | 24 ------------------- mindspore/ops/_op_impl/aicpu/rnnt_loss.py | 2 -- mindspore/ops/_op_impl/aicpu/squeeze.py | 12 ---------- .../ops/_op_impl/aicpu/standard_laplace.py | 1 - .../ops/_op_impl/aicpu/standard_normal.py | 1 - mindspore/ops/_op_impl/aicpu/trans_data.py | 2 -- mindspore/ops/_op_impl/aicpu/uniform_int.py | 1 - mindspore/ops/_op_impl/aicpu/uniform_real.py | 1 - 18 files changed, 1 insertion(+), 102 deletions(-) diff --git a/mindspore/ops/_op_impl/aicpu/ctc_greedy_decoder.py b/mindspore/ops/_op_impl/aicpu/ctc_greedy_decoder.py index 897bc64aa1..8b77d82b86 100644 --- a/mindspore/ops/_op_impl/aicpu/ctc_greedy_decoder.py +++ b/mindspore/ops/_op_impl/aicpu/ctc_greedy_decoder.py @@ -27,10 +27,6 @@ ctc_greedy_decoder_op_info = AiCPURegOp("CTCGreedyDecoder") \ DataType.I64_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.I32_Default, DataType.I64_Default, DataType.I64_Default, DataType.I64_Default, DataType.F64_Default) \ - .dtype_format(DataType.F32_NCHW, DataType.I32_NCHW, DataType.I64_NCHW, DataType.I64_NCHW, - DataType.I64_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.I32_NCHW, DataType.I64_NCHW, DataType.I64_NCHW, - DataType.I64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(ctc_greedy_decoder_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/ctcloss.py b/mindspore/ops/_op_impl/aicpu/ctcloss.py index c393cb04b6..36ca702401 100644 --- a/mindspore/ops/_op_impl/aicpu/ctcloss.py +++ b/mindspore/ops/_op_impl/aicpu/ctcloss.py @@ -30,10 +30,6 @@ ctcloss_op_info = AiCPURegOp("CTCLoss") \ DataType.F32_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.I64_Default, DataType.I32_Default, DataType.I32_Default, DataType.F64_Default, DataType.F64_Default) \ - .dtype_format(DataType.F32_NCHW, DataType.I64_NCHW, DataType.I32_NCHW, DataType.I32_NCHW, - DataType.F32_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.I64_NCHW, DataType.I32_NCHW, DataType.I32_NCHW, - DataType.F64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(ctcloss_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/dropout_genmask.py b/mindspore/ops/_op_impl/aicpu/dropout_genmask.py index 96707a5010..9fdfe7359e 100644 --- a/mindspore/ops/_op_impl/aicpu/dropout_genmask.py +++ b/mindspore/ops/_op_impl/aicpu/dropout_genmask.py @@ -23,7 +23,7 @@ dropout_genmask_op_info = AiCPURegOp("DropoutGenMask") \ .output(0, "y", "required") \ .attr("Seed0", "int") \ .attr("Seed1", "int") \ - .dtype_format(DataType.I32_NCHW, DataType.F16_NCHW, DataType.U8_NCHW) \ + .dtype_format(DataType.I32_Default, DataType.F16_Default, DataType.U8_Default) \ .get_op_info() @op_info_register(dropout_genmask_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/expand_dims.py b/mindspore/ops/_op_impl/aicpu/expand_dims.py index e1a79f24da..61a7d84e46 100644 --- a/mindspore/ops/_op_impl/aicpu/expand_dims.py +++ b/mindspore/ops/_op_impl/aicpu/expand_dims.py @@ -32,18 +32,6 @@ expand_dims_op_info = AiCPURegOp("ExpandDims") \ .dtype_format(DataType.F16_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.F64_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(expand_dims_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/flatten.py b/mindspore/ops/_op_impl/aicpu/flatten.py index dd6c2e9124..926d50fadc 100644 --- a/mindspore/ops/_op_impl/aicpu/flatten.py +++ b/mindspore/ops/_op_impl/aicpu/flatten.py @@ -30,16 +30,6 @@ flatten_op_info = AiCPURegOp("Flatten") \ .dtype_format(DataType.U64_Default, DataType.U64_Default) \ .dtype_format(DataType.F16_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.F32_Default) \ - .dtype_format(DataType.I8_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.F32_NCHW) \ .get_op_info() @op_info_register(flatten_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/gamma.py b/mindspore/ops/_op_impl/aicpu/gamma.py index 801ae41d6a..147c909c20 100644 --- a/mindspore/ops/_op_impl/aicpu/gamma.py +++ b/mindspore/ops/_op_impl/aicpu/gamma.py @@ -25,7 +25,6 @@ gamma_op_info = AiCPURegOp("Gamma") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.F32_Default, DataType.F32_Default, DataType.F32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.F32_NCHW, DataType.F32_NCHW, DataType.F32_NCHW) \ .get_op_info() @op_info_register(gamma_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/is_finite.py b/mindspore/ops/_op_impl/aicpu/is_finite.py index 3a3f8e07ae..33ab3e5447 100644 --- a/mindspore/ops/_op_impl/aicpu/is_finite.py +++ b/mindspore/ops/_op_impl/aicpu/is_finite.py @@ -32,18 +32,6 @@ is_finite_op_info = AiCPURegOp("IsFinite") \ .dtype_format(DataType.F16_Default, DataType.BOOL_Default) \ .dtype_format(DataType.F32_Default, DataType.BOOL_Default) \ .dtype_format(DataType.F64_Default, DataType.BOOL_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.BOOL_NCHW) \ .get_op_info() @op_info_register(is_finite_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/poisson.py b/mindspore/ops/_op_impl/aicpu/poisson.py index 4569efe40e..41e3d10c6a 100644 --- a/mindspore/ops/_op_impl/aicpu/poisson.py +++ b/mindspore/ops/_op_impl/aicpu/poisson.py @@ -24,7 +24,6 @@ poisson_op_info = AiCPURegOp("Poisson") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.F32_Default, DataType.I32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.F32_NCHW, DataType.I32_NCHW) \ .get_op_info() @op_info_register(poisson_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/random_choice_with_mask.py b/mindspore/ops/_op_impl/aicpu/random_choice_with_mask.py index a0eabbc4bc..260b9f5f77 100644 --- a/mindspore/ops/_op_impl/aicpu/random_choice_with_mask.py +++ b/mindspore/ops/_op_impl/aicpu/random_choice_with_mask.py @@ -24,7 +24,6 @@ random_choice_with_mask_op_info = AiCPURegOp("RandomChoiceWithMask") \ .attr("count", "int") \ .attr("seed", "int") \ .attr("seed2", "int") \ - .dtype_format(DataType.BOOL_NCHW, DataType.I32_NCHW, DataType.BOOL_NCHW) \ .dtype_format(DataType.BOOL_Default, DataType.I32_Default, DataType.BOOL_Default) \ .get_op_info() diff --git a/mindspore/ops/_op_impl/aicpu/reshape.py b/mindspore/ops/_op_impl/aicpu/reshape.py index 47d1ea2f75..c10e4540d9 100644 --- a/mindspore/ops/_op_impl/aicpu/reshape.py +++ b/mindspore/ops/_op_impl/aicpu/reshape.py @@ -32,18 +32,6 @@ reshape_op_info = AiCPURegOp("Reshape") \ .dtype_format(DataType.F16_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.F64_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(reshape_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/reverse_sequence.py b/mindspore/ops/_op_impl/aicpu/reverse_sequence.py index 0882bb9a61..3e08ecfbe8 100644 --- a/mindspore/ops/_op_impl/aicpu/reverse_sequence.py +++ b/mindspore/ops/_op_impl/aicpu/reverse_sequence.py @@ -35,18 +35,6 @@ reverse_sequence_op_info = AiCPURegOp("ReverseSequence") \ .dtype_format(DataType.F16_Default, DataType.I32_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.I32_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.I32_Default, DataType.F64_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.I32_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.I32_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I32_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I32_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.I32_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.I32_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.I32_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.I32_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.I32_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.I32_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.I32_NCHW, DataType.F64_NCHW) \ .dtype_format(DataType.BOOL_Default, DataType.I64_Default, DataType.BOOL_Default) \ .dtype_format(DataType.I8_Default, DataType.I64_Default, DataType.I8_Default) \ .dtype_format(DataType.I16_Default, DataType.I64_Default, DataType.I16_Default) \ @@ -59,18 +47,6 @@ reverse_sequence_op_info = AiCPURegOp("ReverseSequence") \ .dtype_format(DataType.F16_Default, DataType.I64_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.I64_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.I64_Default, DataType.F64_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.I64_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.I64_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I64_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I64_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I64_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.I64_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.I64_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.I64_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.I64_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.I64_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.I64_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.I64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(reverse_sequence_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/rnnt_loss.py b/mindspore/ops/_op_impl/aicpu/rnnt_loss.py index d35d102048..8a6bfa51cf 100644 --- a/mindspore/ops/_op_impl/aicpu/rnnt_loss.py +++ b/mindspore/ops/_op_impl/aicpu/rnnt_loss.py @@ -25,8 +25,6 @@ rnnt_loss_op_info = AiCPURegOp("RNNTLoss") \ .output(0, "costs", "required") \ .output(1, "grads", "required") \ .attr("blank_label", "int") \ - .dtype_format(DataType.F32_NCHW, DataType.I32_NCHW, DataType.I32_NCHW, DataType.I32_NCHW, DataType.F32_NCHW, - DataType.F32_NCHW) \ .dtype_format(DataType.F32_Default, DataType.I32_Default, DataType.I32_Default, DataType.I32_Default, DataType.F32_Default, DataType.F32_Default) \ .get_op_info() diff --git a/mindspore/ops/_op_impl/aicpu/squeeze.py b/mindspore/ops/_op_impl/aicpu/squeeze.py index 0172ec5c39..a641d79cd2 100644 --- a/mindspore/ops/_op_impl/aicpu/squeeze.py +++ b/mindspore/ops/_op_impl/aicpu/squeeze.py @@ -32,18 +32,6 @@ squeeze_op_info = AiCPURegOp("Squeeze") \ .dtype_format(DataType.F16_Default, DataType.F16_Default) \ .dtype_format(DataType.F32_Default, DataType.F32_Default) \ .dtype_format(DataType.F64_Default, DataType.F64_Default) \ - .dtype_format(DataType.BOOL_NCHW, DataType.BOOL_NCHW) \ - .dtype_format(DataType.I8_NCHW, DataType.I8_NCHW) \ - .dtype_format(DataType.I16_NCHW, DataType.I16_NCHW) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW) \ - .dtype_format(DataType.I64_NCHW, DataType.I64_NCHW) \ - .dtype_format(DataType.U8_NCHW, DataType.U8_NCHW) \ - .dtype_format(DataType.U16_NCHW, DataType.U16_NCHW) \ - .dtype_format(DataType.U32_NCHW, DataType.U32_NCHW) \ - .dtype_format(DataType.U64_NCHW, DataType.U64_NCHW) \ - .dtype_format(DataType.F16_NCHW, DataType.F16_NCHW) \ - .dtype_format(DataType.F32_NCHW, DataType.F32_NCHW) \ - .dtype_format(DataType.F64_NCHW, DataType.F64_NCHW) \ .get_op_info() @op_info_register(squeeze_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/standard_laplace.py b/mindspore/ops/_op_impl/aicpu/standard_laplace.py index b18c3a5055..e62e440a14 100644 --- a/mindspore/ops/_op_impl/aicpu/standard_laplace.py +++ b/mindspore/ops/_op_impl/aicpu/standard_laplace.py @@ -23,7 +23,6 @@ laplace_op_info = AiCPURegOp("StandardLaplace") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.F32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.F32_NCHW) \ .get_op_info() @op_info_register(laplace_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/standard_normal.py b/mindspore/ops/_op_impl/aicpu/standard_normal.py index 5f5d571913..a3c887d407 100644 --- a/mindspore/ops/_op_impl/aicpu/standard_normal.py +++ b/mindspore/ops/_op_impl/aicpu/standard_normal.py @@ -23,7 +23,6 @@ normal_op_info = AiCPURegOp("StandardNormal") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.F32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.F32_NCHW) \ .get_op_info() @op_info_register(normal_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/trans_data.py b/mindspore/ops/_op_impl/aicpu/trans_data.py index 8f3fe0503d..6ceb905caf 100644 --- a/mindspore/ops/_op_impl/aicpu/trans_data.py +++ b/mindspore/ops/_op_impl/aicpu/trans_data.py @@ -22,8 +22,6 @@ trans_data_op_info = AiCPURegOp("TransData") \ .output(0, "dst", "required") \ .attr("src_format", "str") \ .attr("dst_format", "str") \ - .dtype_format(DataType.U16_NCHW, DataType.U16_5HD) \ - .dtype_format(DataType.U16_5HD, DataType.U16_NCHW) \ .dtype_format(DataType.U16_Default, DataType.U16_5HD) \ .dtype_format(DataType.U16_5HD, DataType.U16_Default) \ .get_op_info() diff --git a/mindspore/ops/_op_impl/aicpu/uniform_int.py b/mindspore/ops/_op_impl/aicpu/uniform_int.py index 3e76dc794a..c2c6b9df45 100644 --- a/mindspore/ops/_op_impl/aicpu/uniform_int.py +++ b/mindspore/ops/_op_impl/aicpu/uniform_int.py @@ -25,7 +25,6 @@ uniform_int_op_info = AiCPURegOp("UniformInt") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.I32_Default, DataType.I32_Default, DataType.I32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.I32_NCHW, DataType.I32_NCHW, DataType.I32_NCHW) \ .get_op_info() @op_info_register(uniform_int_op_info) diff --git a/mindspore/ops/_op_impl/aicpu/uniform_real.py b/mindspore/ops/_op_impl/aicpu/uniform_real.py index 9e0876d317..9b30ace505 100644 --- a/mindspore/ops/_op_impl/aicpu/uniform_real.py +++ b/mindspore/ops/_op_impl/aicpu/uniform_real.py @@ -23,7 +23,6 @@ uniform_real_op_info = AiCPURegOp("UniformReal") \ .attr("seed", "int") \ .attr("seed2", "int") \ .dtype_format(DataType.I32_Default, DataType.F32_Default) \ - .dtype_format(DataType.I32_NCHW, DataType.F32_NCHW) \ .get_op_info() @op_info_register(uniform_real_op_info)